Method and apparatus for encoding and decoding a turbo code in an integrated modem system

A system comprising:

• an encoder to receive a stream of input bits to generate encoded bits from the input bits, the encoded bits forming an Inphase (I) and quadrature (Q) symbols the encoder comprising an interleaver to interleave and delay the input bits, and a serial-to-parallel converter to pair consecutive bits of one of the interleaved and delayed input bits;
• a sync inserter coupled to the encoder to insert synchronizing pattern into the encoded bits, the sync inserter generating output bits;
• and
• a latch and routing circuit coupled to the encoder and the sync inserter to latch the input and output bits and to route signal paths bypassing the encoder and the sync inserter.

An apparatus comprising:

• a sync search engine coupled to receive channel symbols representing a plurality of encoded bits to detect a synchronizing pattern using search, trial lock, and lock states, the sync search engine extracting code symbols from the channel symbols;
• an input buffer coupled to the sync search engine to store the extracted code symbols;
• a first soft-in-soft-out (SISO1) coupled to the input buffer to generate a first soft decision set based on the extracted code symbols;
• an interleaver coupled to the SISO1 to interleave the first soft decision set;
• a second soft-in-soft-out (SISO2) coupled to the input buffer and the interleaver to generate a second soft decision set;
• a de-interleaver coupled to the SISO2 to de-interleave the second soft decision set;
• and
• an adder coupled to the SISO1 and the de-interleaver to generate a hard decision set.

A method comprising:

• detecting a synchronizing pattern by a sync search engine using search, trial lock, and lock states, the sync search engine extracting code symbols from channel symbols representing a plurality of encoded bits;
• storing the extracted code symbols in an input buffer;
• generating a first soft decision set based on the extracted code symbols by a first soft-in-soft-out (SISO1);
• interleaving the first soft decision set by an interleaver;
• generating a second soft decision set by a second soft-in-soft-out (SISO2);
• de-interleaving the second soft decision set by a de-interleaver;
• and
• generating a hard decision set by an adder.

A system comprising:

• an encoder to encode input bits using a turbo code, the encoder comprising:
• an interleaver to interleave and delay a block of the input bits, the interleaver generating interleaved input bits and delayed input bits,
• a serial-to-parallel converter coupled to the interleaver to pair consecutive bits of one of the interleaved and delayed input bits;
• a first encoder coupled to the serial-to-parallel converter to generate a first, second, and third encoded bits from the paired bits,
• a second encoder coupled to the serial-to-parallel converter to generate a fourth encoded bit from the paired bits, and
• a symbol generator coupled to the first and second rate encoders to generate a plurality of symbols, the symbols corresponding to combinations of input bits;
• and
• a modulator coupled to the encoder to modulate the plurality of symbols, the modulator generating encoded bits corresponding to the plurality of symbols.

A system comprising:

• a demodulator to demodulate a stream of encoded bits, the demodulator generating channel symbols representing the encoded bits;
• and
• a decoder coupled to the demodulator to decode the channel symbols, the decoder comprising:
• a sync search engine coupled to receive the channel symbols to detect a synchronizing pattern using search, trial lock, and lock, the sync search engine extracting code symbols from the channel symbols,
• an input buffer coupled to the sync search engine to store the extracted code symbols,
• a first soft-in-soft-out (SISO1) coupled to the input buffer to generate a first soft decision set based on the extracted code symbols,
• an interleaver coupled to the SISO1 to interleave the first soft decision set,
• a second soft-in-soft-out (SISO2) coupled to the input buffer and the interleaver to generate a second soft decision set,
• a de-interleaver coupled to the SISO2 to de-interleave the second soft decision set, and
• an adder coupled to the SISO1 and the de-interleaver to generate a hard decision set.