Vertically stacked field programmable nonvolatile memory and method of fabrication
AssigneeMatrix Semiconductor, Inc.
InventorsMark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
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Abstract
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Claims20
A 3-dimensional memory array built above a substrate, the memory array comprising:
- N layers of memory cells;
- N+1 layers of conductors;
- said memory cells and conductors fabricated using no more than N+1 masks.
A 3-dimensional memory built above a substrate, the memory comprising:
- N layers of memory cells;
- N+1 layers of conductors;
- at least one contact connecting each of the layers of conductors to the substrate;
- said memory cells, conductors and contacts being fabricated with no more than 2N+1 masks.
A 3-dimensional memory built above a monocrystalline substrate, the memory comprising:
- N layers of memory cells, each memory cell comprising a state change element and a steering element;
- N+1 layers of conductors shared between successive memory cell layers and
- arranged such that a vertical projection of a first conductor in a first layer intersects a second conductor in a second layer;
- at least one contact connecting each conductor to the substrate;
- said memory cells, conductors and contacts being fabricated with no more than 2N+1masks.
A 3-dimensional memory built above a monocrystalline substrate, the memory comprising:
- N layers of memory cells, each memory cell comprising a state change element and a steering element;
- N+1 layers of conductors shared between successive memory cell layers and arranged such that a vertical projection of a first conductor in a first layer intersects a second conductor in a second layer, and a memory cell is formed between said first and second conductors at the projection;
- at least one contact connecting each conductor to the substrate;
- said memory cells, conductors and contacts being fabricated with no more than N+2 masks.
Dependencies are inferred from the claim text.