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US 6,483,156 B1Granted
Double planar gated SOI MOSFET structure
AssigneeInternational Business Machines Corporation
InventorsJames W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson, Jed H. Rankin
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Abstract
A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.
Claims7
A FET comprising:
- a substrate;
- a source region and a drain region in the substrate, each of said source region and said drain region having a top, bottom, and at least two side diffusion surfaces, the source and drain regions separated by a channel region having a top, bottom and side channel surfaces substantially coplanar with corresponding ones of the diffusion surfaces;
- a gate adjacent the top and the side channel surfaces and electrically insulated from the top and side channel surfaces;
- and
- a dielectric material in the gate for electrically separating the gate into two electrically isolated portions, each having a substantially coplanar top surface.
2 more elements
Dependencies are inferred from the claim text.