Circuit pattern design method, exposure method, charged-particle beam exposure system

A circuit pattern design method for generating a circuit pattern from a logic description which describes circuit operation of a semiconductor device in a charged-particle beam exposure system having

• a charged-particle beam exposure apparatus for forming a pattern on a sample by charged-particle beam exposure using both a character projection exposure method and a variable shaped beam exposure method,
• a standard cell library which stores standard cells that optimize circuit patterns for function units, and
• a CP aperture mask management table which stores an index unique to each aperture block that is formed on an aperture mask used for exposure by the character projection exposure method and bears characters corresponding to the standard cells, information of the standard cells corresponding to the characters laid out on each aperture block, and the number of charged-particle beam shots necessary to expose all the characters corresponding to the standard cells by the character projection exposure method, comprising:
• the step of generating a circuit pattern from the logic description for each aperture block by using standard cells corresponding to characters formed in each aperture block, and associating each circuit pattern with an aperture block used to generate the circuit pattern;
• the step of extracting a circuit pattern which satisfies a predetermined constraint condition from a plurality of generated circuit patterns;
• and
• the step of selecting a circuit pattern that requires the smallest number of charged-particle beam irradiation operations when charged-particle beam exposure is performed by using an aperture block corresponding to the extracted circuit pattern.