Method and system for proactively debugging fitting problems in programmable logic devices

A computer implemented method of debugging fitting problems comprising the steps of:

• a) in response to an programmable logic device (PLD) design failing a first fitting on a first programmable device, automatically selecting a second programmable device having more resources than said first programmable device but having a same pin package;
• b) automatically performing a second fitting of said PLD design on said second programmable device which, if successful, yields a determined pin assignment;
• c) automatically performing a third fitting of said PLD design on said first programmable device and constrained by said determined pin assignment;
• and
• d) provided said third fitting generates fitting problems, automatically performing a fourth fitting of said PLD design on said first programmable device and constrained by said determined pin assignment but allowing failing pins to float.

A system comprising a processor coupled to a bus and memory coupled to said bus wherein said memory contains processor instructions for implementing a method of debugging fitting problems, said method comprising the steps of:

• a) in response to an programmable logic device (PLD) design failing a first fitting on a first programmable device, automatically selecting a second programmable device having more resources than said first programmable device but having a same pin package;
• b) automatically performing a second fitting of said PLD design on said second programmable device which, if successful, yields a determined pin assignment;
• and
• c) automatically performing a third fitting of said PLD design on said first programmable device and constrained by said determined pin assignment.