Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

A method for observing logic element signals in a programmable logic device, comprising:

• providing a plurality of logic element registers having outputs;
• providing a plurality of programmable logic circuits;
• arranging a plurality of regular memory cells in a first-in-first-out chain;
• arranging a plurality of shadow memory cells in a first-in-first out chain that are not directly connected to any programmable logic circuits to configure logic in those programmable logic circuits;
• connecting each of a plurality of load transistors between one of the register outputs and one of the shadow memory cells;
• connecting a test register to the first-in-first-out chain of shadow memory cells and to the first-in-first-out chain of regular memory cells;
• receiving signals with the logic element registers and providing corresponding logic element signals at the register outputs;
• applying a memory cell output signal from each regular memory cell to a respective one of the programmable logic circuits to configure logic in that programmable logic circuit;
• selectively conveying logic element signals to be observed from the outputs of the registers to the shadow memory cells using the load transistors;
• and
• receiving the logic element signals to be observed from the shadow memory cells using the test register.

A method for observing logic signals in a programmable logic device comprising:

• providing a plurality of programmable logic circuits;
• arranging a plurality of memory cells arranged in an array of rows and columns, each memory cell having an output connected to one of the programmable logic circuits;
• associating each of a plurality of address lines with one of the columns of memory cells;
• associating each of a plurality of data lines with one of the rows of memory cells;
• connecting at least one debug output line connected to a test register;
• providing a plurality of pass transistors, each controlled by one of the data lines and each coupled to one of the programmable logic circuits and connected to the debug output line;
• providing logic signals with the programmable logic circuits;
• supplying output signals from the memory cells to the programmable logic circuits to which those memory cells are connected to configure programmable logic in those programmable logic circuits;
• addressing the memory cells in a given column using the address line associated with that column;
• providing programming data to the memory cells in the given column using the data lines;
• and
• selectively passing the logic signals from the programmable logic circuits to the debug output line using the pass transistors;
• and
• passing those logic signals to the test register with the debug output line.

A method for observing logic signals from programmable logic circuits comprising:

• arranging a plurality of programmable logic circuits in rows and columns in a programmable logic device;
• arranging a plurality of memory cells in an array of rows and columns that provide memory cell output signals that are applied to the programmable logic circuits to configure programmable logic within the programmable logic circuits;
• associating each of a plurality of address lines with one of the columns of memory cells for addressing the memory cells in that column;
• associating each of a plurality of data lines with one of the rows of memory cells for providing programming data to the memory cells in that row wherein at least some of which are associated with particular rows of the programmable logic circuits;
• providing a test register;
• associating each of a plurality of sense lines with one of the columns of the programmable logic circuits;
• controlling each of a plurality of access transistors with one of the data lines that is associated with one of the rows of programmable logic circuits;
• connecting each of the access transistors between one of the programmable logic circuits in a given column and the sense line associated with that column;
• routing signals to the test register from the sense lines using circuitry;
• providing logic signals with the programmable logic circuits;
• activating a given data line;
• and
• routing logic signals from the programmable logic circuits to which the access transistors associated with the given data line are connected to the test register using the sense lines and circuitry for routing.

A method for observing logic signals from programmable logic circuits comprising:

• using a plurality of programmable logic circuits on a programmable logic device;
• arranging a plurality of memory cells in an array of rows and columns to provide memory cell output signals that are applied to the programmable logic circuits to configure programmable logic within the programmable logic circuits;
• connecting a plurality of address registers including at least one debug register in at least one chain;
• associating each of a plurality of data lines with one of the rows of memory cells for providing programming data to the memory cells in that row;
• associating at least some of the data lines with particular ones of the programmable logic circuits;
• associating each of a plurality of access transistors with one of the particular programmable logic circuits;
• connecting each of the access transistors between an output of that programmable logic circuit and one of the data lines associated with the particular programmable logic circuits;
• connecting a test register to at least the data lines that are associated with the particular programmable logic circuits;
• providing logic signals with the programmable logic circuits;
• and
• turning on at least one of the access transistors with signals from the debug address register when it is desired to observe logic signals from the programmable logic circuit connected to that access transistor so that those logic signals are provided to the test register by the data lines connected to that access transistor.