Functional verification of both cycle-based and non-cycle based designs

A method of verifying a design containing at least combinatorial logic loop, wherein said combinatorial logic loop is to be evaluated until a condition is attained, said method comprising:

• (a) partitioning said design into a plurality of clusters, wherein each of said plurality of clusters contains a plurality of combinatorial blocks capable of being evaluated in parallel by a plurality of evaluation units in response to receiving a cluster number uniquely identifying a corresponding cluster;
• (b) storing a plurality of flow control instructions indicating a sequence in which said plurality of clusters are to be evaluated;
• and
• (c) sending each of a sequence of cluster numbers to said plurality of evaluation units to cause the combinatorial blocks in a corresponding cluster to be evaluated, whereby said design is verified.

A verification system enabling functional verification of a non-cycle based design containing at least combinatorial logic loop, wherein said combinatorial logic loop is to be evaluated until a condition is attained, said verification system comprising:

• means for partitioning said non-cycle based design into a plurality of clusters, wherein each of said plurality of clusters contains a plurality of combinatorial blocks capable of being evaluated in parallel by a plurality of evaluation units in response to receiving a cluster number uniquely identifying a corresponding cluster;
• means for setting a register to reflect an initial condition associated with said combinatorial logic loop;
• first storing means for storing data indicating the manner in which said register is to be modified upon evaluation of a combinatorial block contained in said combinatorial logic loop;
• second storing means for storing a plurality of flow control instructions indicating a sequence m which said plurality of clusters are to be evaluated depending on a status of said register, wherein at least one of said flow control instructions specifies when the evaluation of clusters representing said combinatorial logic loop is to end;
• means for sending each of a sequence of cluster numbers to said plurality of evaluation units to cause the combinatorial blocks in a corresponding cluster to be evaluated;
• means for modifying said register according to said data stored by said means for storing, wherein said sending and modifying are continued until the evaluation of said combinatorial logic loop ends,
• whereby said non-cycle based design is verified based on the evaluation of said combinatorial logic loop.

A verification system enabling functional verification of a design, said verification system comprising:

• a plurality of evaluation units, with each evaluation unit being capable of evaluating one of a plurality of combinatorial blocks within a cluster in response to receiving a cluster number identifying the corresponding cluster, a plurality of clusters together specifying said design including data dependencies;
• a flow control memory storing a plurality of flow control instructions indicating a sequence in which said plurality of clusters are to be evaluated;
• and
• a flow processor sending a sequence of cluster numbers to said plurality of evaluation units to cause said design to be evaluated.