US 6,480,987 B1 · Method and system for estimating capacitive coupling in a hierarchical design

Abstract

A coupling capacitance analysis logic allows the classification of capacitance in a hierarchical electronic design. The coupling capacitance analysis logic analyzes capacitance between signal lines and other signal lines, and analyzes capacitance between signal lines and the substrate on which the circuitry resides, between signal lines and transistor gates, and between signal lines and diffusion regions. Capacitances associated with child blocks within the hierarchical design are first analyzed and then brought up into higher levels of the design without the need to repeat the analysis performed in the lower level. In this manner, a complex hierarchical design may be effectively and efficiently analyzed. Once the design analysis is complete, the logic of the invention determines the amount of coupling capacitance attributable to each signal in the design with respect to each subject signal. Each signal will be analyzed as the subject signal and each signal affecting the subject signal will be a culprit signal. For each subject signal, the weighted average of all culprit signals is determined by multiplying the rise and fall times of each culprit signal by the coupling capacitance attributable to that culprit signal. This is performed for each culprit signal affecting the subject signal. The total is then divided by the total coupling capacitance between the subject signal and all culprit signals, resulting in the weighted average of all culprit signals affecting the subject signal. All signals in the design are analyzed as the subject signal.

Claims15

Dependent claims

A method for estimating capacitive coupling in a hierarchical design, the method comprising the steps of:

providing a circuit having a first level and a second level;
providing a first signal associated with said circuit;
providing at least one additional signal associated with said circuit, said additional signal coupled to said first signal;
determining a coupling capacitance between said first signal and said additional signal, said coupling capacitance determined with respect to said first level, resulting in a first level coupling capacitance, and with respect to said second level, resulting in a second level coupling capacitance;
and
adding said first level coupling capacitance to said second level coupling capacitance to determine a total coupling capacitance between said first signal and said additional signal.

3 more elements

A computer readable medium having a program for estimating capacitive coupling in a hierarchical design, the program comprising:

logic configured to receive a circuit having a first level and a second level;
logic configured to provide a first signal in said circuit;
logic configured to provide at least one additional signal in said circuit, said additional signal coupled to said first signal;
logic configured to determine a coupling capacitance between said first signal and said additional signal, said coupling capacitance determined with respect to said first level, resulting in a first level coupling capacitance, and with respect to said second level, resulting in a second level coupling capacitance;
and
logic configured to add said first level coupling capacitance to said second level coupling capacitance to determine a total coupling capacitance between said first signal and said additional signal.

3 more elements

Dependencies are inferred from the claim text.

Method and system for estimating capacitive coupling in a hierarchical design

Life of this patent

Method and system for estimating capacitive coupling in a hierarchical design

Life of this patent

Abstract

Claims15