US 6,480,985 B1 · Method and apparatus for graphically presenting an integrated circuit design

Abstract

Briefly, the present invention analyzes high-level IC description language code, such as VHDL and Verilog, of an integrated circuit (IC) design and generates graphical representations of the IC design based on the code analyzed. The graphical representations can include one or more of the following: 1) a block diagram of functional blocks; 2) a state diagram of a state machine; and 3) a flow chart of an operation al flow of the IC. Graphical representations provide more understandable representations of circuits described by the high-level IC description language code than the code itself.

Claims33

Dependent claims

A computer-implemented method comprising:

extracting, from high-level IC description language code, representation information corresponding to a) functional blocks of an IC design, b) a state machine, and c) an operation flow of the IC design;
and
generating a graphical representation of the IC design based on the extracted representation information, wherein the graphical representation comprises a block diagram for the functional blocks of the IC design, a state diagram for the state machine, and a flow chart for the operation flow of the IC design.

Dependencies are inferred from the claim text.

Method and apparatus for graphically presenting an integrated circuit design

Life of this patent

Method and apparatus for graphically presenting an integrated circuit design

Life of this patent

Abstract

Claims33