Computer RAM memory system with enhanced scrubbing and sparing

A method for correcting and detecting errors in a computer memory system, wherein said computer memory system comprises at least one row of memory chips, further wherein data is fetched from said computer memory chips in parallel and each memory chip in said chip row corresponds to a different bit position in said fetched data, comprising:

• initializing at least one error counter, each error counter corresponding to a memory chip, said error counter being incremented where a single-bit error is detected in said corresponding memory chip;
• scrubbing said chip row, said scrubbing including correcting single bit errors;
• modifying the value of a register in response to said error counter exceeding a threshold, said modification indicating a change to half spare mode, said half spare mode comprising:
• reinitializing said error counter,
• performing a second scrubbing of said chip row,
• storing a SPUE pattern to a storage location of said chip row wherein
• said storage location is detected as containing a multi-bit error,
• sparing a chip in said chip row wherein said error counter corresponding to said chip exceeds a threshold;
• modifying the value of said register, said modification indicating a change to full spare mode, said full spare mode comprising:
• reinitializing said error counter,
• scrubbing said chip row;
• and
• modifying the value of said register in response to said error counter exceeding a threshold, said modification indicating a change to half spare mode.

A method of detecting and correcting errors in a computer memory system, comprising:

• scrubbing a chip row of said computer memory, said scrubbing including detecting single-bit and multi-bit errors, said scrubbing also including correcting single-bit errors;
• incrementing the value of a counter in response to the detection of an error during said scrubbing;
• modifying the value of a register in response to said counter value exceeding a threshold, said modification indicating a change to half spare mode, said half spare mode causing a request to write first data to a defective location in said chip row to result in the writing of said data to both said defective location and to a spare memory location, further wherein a request to fetch a second data from a defective location in said chip row causes the fetching of said second data from said defective location;
• scrubbing said chip row in response to said indication of half spare mode, said scrubbing including detecting single-bit and multi-bit errors and correcting single bit errors, wherein the detection of a multi-bit error causes a SPUE pattern to stored to the memory location containing the uncorrectable error;
• sparing a chip in said chip row where a counter value corresponding to said chip exceeds a threshold;
• modifying the value of said register in response to the completion of said half mode, said modification indicating a change to full spare mode, said full spare mode causing a request to write a third data to said defective location in said computer memory to result in the writing of said third data to said spare memory location, further wherein a request to fetch a fourth data from a defective location in said computer memory causes the fetching of said fourth data from said spare memory location;
• scrubbing said chip row in response to said indication of full spare mode, said scrubbing including detecting single-bit and multi-bit errors and correcting single bit errors;
• and
• modifying the value of a register in response to said counter value exceeding a threshold, said modification indicating a change to half spare mode.

A method of detecting and correcting errors in a computer memory system, comprising:

• initiating a first mode of operation in response to the identification of a first portion of a first computer memory and/or a first portion of a second computer memory as being defective, said first mode of operation further comprising:
• scrubbing at least one of the following:
• said first portion of first computer memory, said first portion of first computer memory not having previously been spared, or
• said first portion of second computer memory, said first portion of second computer memory having previously been substituted for spared first and/or second computer memory, and
• sparing said first portion of first computer memory and/or said first portion of second computer memory with a second portion of second computer memory, said spared first portions of first and/or second computer memory having been identified as being defective during said first mode scrubbing,
• wherein the detection of an unrecoverable error in said first portions of first and/or second memory during said first mode scrubbing causes the storing of a SPUE pattern in said first portions of first and/or second computer memory containing said unrecoverable error, further wherein a request to write a first data to said defective portions of first and/or second computer memory causes the writing of said first data to said defective portions of first and/or second computer memory and to said second portion of second computer memory, further wherein a request to fetch a second data from said defective portions of first and/or second computer memory causes the fetching of said second data from said defective portions of first and/or second computer memory;
• and
• initiating a second mode of operation in response to the completion of said first mode of operation, said second mode of operation further comprising:
• scrubbing said first portions of first and/or second computer memory, scrubbing said second portion of second computer memory, and
• initiating said first mode of operation in response to the identification of defective first and/or second computer memory by said second mode scrubbing,
• wherein a request to write a third data to said defective portions of first and/or second computer memory causes the writing of said third data to said second portion of second computer memory, further wherein a request to fetch a fourth data from said defective portions of first and/or second computer memory causes the fetching of said fourth data from said second portion of second computer memory.