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US 6,480,980 B2Granted
Combinational test pattern generation method and apparatus
AssigneeNEC Electronics Corporation
InventorWern-Yan Koe
Life of this patent
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Abstract
A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.
Claims26
A method comprising:
- applying a resultant test pattern to at least one combinational logic circuit;
- wherein the resultant test pattern is generated by:
- generating an initialization test pattern;
- generating a change test pattern;
- designating a symbol in the initiation test pattern as a reference symbol;
- generating a reordered initialization test pattern, the generating the reordered initialization test pattern including reordering a sequence of symbols, other than the reference symbol, of the initialization test pattern such that those symbols which are of a value substantially equivalent to a value of the reference symbol appear either in or in slots substantially proximate to a first symbol position slot and such that those symbols which are of a value substantially opposite the value of the reference symbol appear either in or in slots substantially proximate a second symbol position slot.
3 more elements
An apparatus comprising:
- a combinational logic circuit;
- means for providing to the combinational logic, a resultant test pattern that includes a reordered initialization test pattern, the reordered initialization patent being generated from an initiation test pattern having a designated reference symbol, the reordered initialization test pattern being generated by reordering a sequence of symbols, other than the reference symbol, of the initialization test pattern such that those symbols which are of a value substantially equivalent to a value of the reference symbol appear either in or in slots substantially proximate to a first symbol position slot and such that those symbols which are of a value substantially opposite the value of the reference symbol appear either in or in slots substantially proximate a second symbol position slot.
An apparatus comprising:
- at least one register bank;
- a combinational logic circuit having inputs to receive signals from the at least one register bank;
- wherein the at least one registered bank is configured to provide to the combinational logic circuit a resultant test pattern that includes a reordered initialization test pattern and a reordered change test pattern, the reordered initialization test pattern being generated from an initiation test pattern having a designated reference symbol in a tail symbol position slot of the initialization test pattern, the reordered initialization test pattern being generated by reordering a sequence of symbols, other than the reference symbol, of the initialization test pattern such that those symbols which are of a value substantially equivalent to a value of the reference symbol appear either in or in slots substantially proximate to a head symbol position slot and such that those symbols which are of a value substantially opposite the value of the reference symbol appear either in or in slots substantially proximate a tail symbol position slot, wherein the reference symbol is placed in a slot between the head symbol position slot and the tail symbol position slot of the reordered initialization test pattern.
Dependencies are inferred from the claim text.