Semiconductor integrated circuits and efficient parallel test methods
AssigneeOki Electric Industry Co., Ltd.
InventorNobuhiro Tomari
Life of this patent
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Abstract
A semiconductor integrated-circuit device includes both conventional internal circuitry, and a selection circuit that provides external output of signals from the internal circuitry under control of a selection signal. In a parallel test system, the output terminals of a plurality of devices under test are connected to a single set of tester input terminals, at which response signals are received from each device in turn. Alternatively, each device has an internal test circuit that carries out tests in response to test control codes received from a tester, evaluates the response signals from the internal circuitry, makes a pass/fail decision, and provides the tester with the pass/fail result.
Claims9
A method of testing a plurality of semiconductor integrated circuits having respective internal circuitry and respective selection circuits, the internal circuitry receiving control signals, performing functions that the semiconductor integrated circuits provide as a product, and generating response signals, the selection circuits receiving respective external selection signals having a first state and a second state, providing external output of the response signals when said respective external selection signals are in the first state, and blocking external output of the response signals when said respective external selection signals are in the second state, the method comprising the steps of:
- connecting all of the semiconductor integrated circuits in common to a single set of control signal output terminals of a tester, and to a single set of response signal input terminals of the tester;
- connecting each of the semiconductor integrated circuits to a separate selection signal output terminal of the tester, for sending said respective external selection signals to the selection circuits in the semiconductor integrated circuits;
- simultaneously sending said control signals from the tester to all of the semiconductor integrated circuits;
- selecting the semiconductor integrated circuits one by one, by placing their external selections signals in the first state;
- and
- making a pass/fail decision for each said semiconductor integrated circuit among said semiconductor integrated circuits by processing the response signals received from the semiconductor integrated circuit when the semiconductor integrated circuit is selected.
A method of testing a plurality of semiconductor integrated circuits having respective internal circuitry and respective internal test circuits, the internal circuitry receiving control signals, performing functions that the semiconductor integrated circuit provides as a product, and generating response signals, the internal test circuits receiving a first external test control code giving test execution commands, generating said control signals according to the first external test control code, supplying said control signals to the internal circuitry, receiving the response signals from the internal circuitry, making a pass/fail decision according to the response signals, receiving a second external test control code giving a test result output command, and providing external output of the pass/fail decision in response to the second external test control code, the method comprising the steps of:
- (a) sending the first external test control code to the plurality of semiconductor integrated circuits;
- (b) repeating step (a), varying the first external test control code to carry out different tests;
- (c) sending the second external test control code to the plurality of semiconductor integrated circuits;
- and
- (d) receiving the pass/fail decision from each one of the plurality of semiconductor integrated circuits.
A method of testing a plurality of semiconductor integrated circuits having respective internal circuitry, respective internal test circuits, and respective non-volatile memories, the internal circuitry receiving control signals, performing functions that the semiconductor integrated circuit provides as a product, and generating response signals, the internal test circuits receiving an external test control code giving test execution commands, generating said control signals according to the external test control code, supplying said control signals to the internal circuitry, receiving the response signals from the internal circuitry, and making a pass/fail decision according to the response signals, the method comprising the steps of:
- (a) sending the external test control code to the plurality of semiconductor integrated circuits;
- (b) repeating step (a), varying the external control code to carry out different tests;
- (c) storing each pass/fail decision made by said respective internal test circuits in said respective non-volatile memories in the semiconductor integrated circuits;
- and
- (d) receiving the pass/fail decision from each one of the plurality of semiconductor integrated circuits.
Dependencies are inferred from the claim text.