Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons

A probe assembly comprising:

• a channel for communicating with a tester that provides data values for testing a DUT through the channel;
• a plurality of probe elements for contacting a plurality of signal locations of one or more devices under test (DUTs);
• and
• tester-DUT interface circuitry coupled between the channel and the probe elements to receive said data values from the tester and to provide error values to the tester, wherein
• the circuitry forwards said data values to each of the plurality of DUTs via said probe elements, the circuitry performs a first comparison between the values of two locations having corresponding addresses in different DUTs after reading from said locations, and in response generates error values indicative of the first comparison.

An interface circuit for testing a plurality of DUTs, comprising:

• means for receiving a data value and an associated address as part of a test sequence;
• means for writing a plurality of copies of said data value at a plurality of corresponding addresses;
• means for reading from said plurality of corresponding addresses a plurality of read data values;
• and
• means for performing a first comparison between two of said plurality of read data values to generate an error value representing a difference, if any, between two read data values.

An interface circuit for testing a plurality of DUTs, comprising:

• channel port for receiving a data value and an associate address as part of a test sequence;
• a plurality of DUT ports each for reading data values from and writing data values to a separate DUT;
• and
• first logic coupled to the DUT ports for performing an XOR operation upon two or more corresponding bits of two or more data values read from locations having corresponding addresses in different DUTs.

A method for testing a plurality of DUTs, comprising:

• receiving a data value and an associated address as part of a test sequence from a single channel of a tester;
• writing a plurality of copies of said data value at a plurality of corresponding addresses in a plurality of DUTs;
• reading from said plurality of corresponding addresses in said DUTs a plurality of read data values;
• and
• performing first comparisons between pairs of said plurality of read data values to generate error values representing differences between said pairs of read data values.

An integrated circuit test system comprising:

• a tester having at least one set of tester input/output (I/O) lines, the tester to use each set to write a data value to a separate device to be tested;
• and
• a contact assembly having two or more sets of elements, each set of elements to contact a plurality of signal locations of a separate device under test (DUT), the contact assembly further includes circuitry having an input coupled to one set of said tester I/O lines and an output coupled to the two or more sets of elements to provide said data value on each set of said elements,
• the circuitry being further configured to read from each DUT a read data value in response to receiving a read from the tester over the set of I/O lines, compare a read data value from one DUT to a read data value from another DUT to determine an error in one or both of said DUTs, and send an error value, indicative of the error, to the tester over the set of tester I/O lines.

A contact assembly comprising:

• two or more sets of first elements, each set of elements is to contact a plurality of signal locations of a separate device under test (DUT);
• and
• first circuitry having an input to be coupled to one set of I/O lines of a tester and an output coupled to the two or more sets of elements, to provide a write data value, received from the tester over the set of I/O lines, on each set of said elements,
• the circuitry being further configured to read from each DUT a read data value, in response to receiving a read from the tester over the set of I/O lines, compare a read data value from one DUT to that from another DUT to determine an error in one or both DUTs, and send an error value, indicative of the error, to the tester over the set of tester I/O lines.

An interface circuit for use when coupled between an integrated circuit tester and two or more devices under test (DUTs), comprising:

• an input to be coupled to one set of I/O lines of the tester and to receive a write data value from the tester;
• an output to be coupled to two or more sets of elements, where each set of elements is to contact a plurality of signal locations of a separate device under test (DUT), to provide said write data value to each set of elements;
• and
• comparison circuitry to compare a data value read from one DUT in response to receiving a read from the tester to a data value read from another DUT to determine an error in one or both DUTs,
• wherein the circuitry is to send an error value, indicative of the error, to the tester over the set of tester I/O lines.

A method for testing a plurality of devices under test (DUTs), comprising:

• receiving via a set of tester I/O lines a write data value from a tester, the tester to use the set to write a data value to a single device to be tested;
• providing said write data value to each of two or more sets of elements, where each set of elements is contacting a plurality of signal locations of a separate DUT;
• reading a data value from each DUT in response to receiving a read from the tester;
• comparing a read data value from one DUT to a read data value from another DUT to determine an error in one or both of said DUTs;
• and
• sending an error value indicative of the error to the tester over the set of tester I/O lines.