ECC mechanism for set associative cache array

A computer system comprising:

• a processor;
• a memory device;
• a set associative cache array connected to said processor and said memory device, having a plurality of cache blocks for storing values associated with memory blocks of said memory device, said memory blocks being mapped to a plurality of congruence classes each composed of a plurality of said cache blocks;
• and
• means for determining whether cache blocks in a given congruence class collectively contain at least one error, said determining means including means for executing an error correction code based on all bits in the plurality of values in the cache blocks of said given congruence class.

A cache memory, comprising:

• a set associative cache array including a plurality of congruence classes that each contain a plurality of cache blocks storing a plurality of values;
• hit/miss logic, coupled to said associative cache array, that determines whether or not a requested value is stored within the set associative cache array;
• error correction code (ECC) storage that stores a plurality of ECC values that are each associated with a respective entire congruence class among the plurality of congruence classes within the set associative cache array;
• and
• ECC circuitry coupled to the set associative array and the ECC storage, wherein the ECC circuitry determines whether cache blocks in a given congruence class of the set associative cache array collectively contain at least one error based upon an ECC value within the ECC storage associated with the given congruence class and all bits of the plurality of values stored within the cache blocks of the given congruence class.