Multiple module processing system with reset system independent of reset characteristics of the modules

A method of resetting a plurality of processing modules, the method comprising:

• asserting a reset signal in response to a reset command,
• enabling one or more clocks used by the plurality of processing modules for a predetermined number of cycles of a master clock, and
• thereafter
• disabling the one or more clocks, and
• de-asserting the reset signal.

A processing system comprising:

• first and second processing modules having different reset characteristics, each of said first and second processing modules being controlled by a respective module-clock signal and by a reset signal, wherein each processing module is initialized to an initial state in response to the reset signal and performs its processing function upon deactivation of the reset signal,
• a clock module that provides respective first and second module-clock signals to the first and second processing modules in response to a master-clock signal and to a clock-enable signal,
• a controller that provides the clock-enable signal in response to a reset command,
• a reset module that provides the reset signal to the first and second processing modules in response to said reset command and deactivates the reset signal in response to a deactivation of the clock-enable signal by the controller, wherein
• the controller deactivates the clock-enable signal after a number of cycles of the master-clock signal.