Multiport memory, data processor and data processing system

A data processor, comprising:

• a CPU;
• and
• a port expansion circuit;
• said CPU and said port expansion circuit being formed in a semiconductor chip,
• said port expansion circuit being connected to said CPU via an internal bus and connected to access ports of a plurality of RAMs provided outside said semiconductor chip, thereby allowing access to the access ports with said plurality of RAMs being apparently defined as a single multiport memory, said port expansion circuit including,
• an input circuit which allows access control information for operating said plurality of RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles;
• a timing generator which generates a control clock signal capable of prescribing each of said plurality of memory cycle in series plural times during one cycle of a synchronizing clock signal of said data processor;
• and
• a logic circuit capable of sequentially supplying the access control information inputted to said input circuit to said plurality of RAMs in parallel in parts every serial memory cycles synchronized with the control clock signal.

A data processing system, comprising:

• an access control circuit;
• a port expansion circuit;
• and
• a plurality of RAMs;
• said port expansion circuit being connected to said access control circuit and access ports of said plurality of RAMs, thereby allowing access to the access ports with said plurality of RAMs being apparently defined as a single multiport memory, said port expansion circuit including,
• an input circuit which allows access control information for operating said plurality of RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles;
• a timing generator which generates a control clock signal capable of prescribing each of said plurality of memory cycle in series plural times during one cycle of a clock signal supplied from the outside;
• and
• a logic circuit capable of sequentially supplying the access control information inputted to said input circuit to said plurality of RAMs in parallel in parts every serial memory cycles synchronized with the control clock signal.

A semiconductor integrated circuit, comprising:

• a bus master module activated in synchronism with a first clock signal;
• a plurality of RAM modules activated in synchronism with second clock signals having a plurality of phases, which are higher than said first clock signal in frequency;
• and
• a port expansion module which is connected to said bus master module and said plurality of RAM modules and allows said bus master module to be accessed with said plurality of RAM modules as a single multiport memory apparently,
• wherein said bus master module allows access control information for activating said plurality of RAM modules in parallel by a plurality of memory cycles to be outputted, and
• wherein said port expansion module comprises an input circuit which allows the access control information for operating said plurality of RAM modules in parallel every memory cycles to be collectively inputted by a plurality of memory cycles from said bus master module, a timing generator which generates each second clock signal capable of prescribing said each memory cycle in series plural times during one cycle of the first clock signal, and a logic circuit capable of sequentially supplying the access control information inputted to said input circuit to said plurality of RAM modules in parallel in parts every serial memory cycles synchronized with said each second clock signal.

A memory, comprising:

• a plurality of RAMs;
• an input circuit which receives a plurality of pieces of access information for activating said plurality of RAMs therein in parallel in synchronism with a first clock signal;
• and
• a parallel/serial converter which outputs said plurality of pieces of access information to said plurality of RAMs in series every one or two or more access information,
• wherein said parallel/serial converter performs an output operation in synchronism with a second clock signal higher than the first clock signal in frequency, and
• said plurality of RAMs are activated in parallel in synchronism with the second clock signal.