Synchronized FIFO memory circuit
AssigneeSony Corporation
InventorKoji Hirairi
Life of this patent
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Abstract
A synchronized FIFO memory circuit includes a random access memory and a FIFO controller having a decreased critical-path length. The synchronized FIFO circuit comprises a first counter for counting a number representing a Read Pointer, a second counter for counting a number representing a Write Pointer, a third counter for holding and managing the number of remaining empty entries in the FIFO memory circuit, and comparison means for comparing the value of the third counter with a constant value. Write Ready, Read Ready, Full, Empty, Almost Full and Almost Empty which are status signals of the FIFO memory circuit are produced at a high speed by comparison carried out by the comparison means without using a subtractor.
Claims23
A synchronized FIFO memory circuit including a random access memory and a FIFO controller, said circuit further comprising:
- a first counter for counting a number representing a Read Pointer;
- a second counter for counting a number representing a Write Pointer;
- a third counter for holding and managing the number of remaining empty entries of said FIFO memory circuit;
- and
- comparison means for comparing a value of said third counter with a constant value,
- wherein status signals of said FIFO memory circuit, namely, Write Ready, Read Ready, Full, Empty, Almost Full and Almost Empty, are produced at a high speed by comparison carried out by said comparison means.
A synchronized FIFO memory circuit including a random access memory and a FIFO controller, said circuit comprising:
- a first counter, said first counter changing a first number;
- a second counter, said second counter changing a second number;
- a third counter, third counter incrementing a value by an incrementing amount when said first number changes, third counter decrementing said value by a decrementing amount when said second number changes;
- and
- a status signal generator, said status signal generator outputting at least one status signal.
Dependencies are inferred from the claim text.