Content addressable storage apparatus and register mapper architecture

A register mapper configuration comprising:

• a group of function arrays, each of said function arrays being dedicated to execute corresponding specific functions of said register mapper, said function arrays including:
• a storage array and a separate compare array for effecting storage of data and comparisons of said stored data with a plurality of input search vectors, respectively, wherein said storage array is arranged as a plurality of multi-bit entries containing a plurality of bit storage cells, said plurality of bit storage cells including at least first and second bit storage cells, and wherein said first bit storage cell is disposed between said second bit storage cell and said compare array;
• and
• a plurality of bit buses each coupling a respective one of the plurality of bit storage cells in the storage array to the compare array, such that the compare array can concurrently compare all bits within the plurality of multi-bit entries with corresponding bits of said plurality of search vectors.

An integrated circuit, comprising:

• a substrate;
• and
• a content addressable memory (CAM) formed on said substrate, said CAM including:
• a plurality of CAM cells including first and second CAM cells, each of said CAM cells further including a storage portion and a compare portion, wherein:
• said storage portion of each of said plurality of CAM cells is arranged in a first array, wherein the storage portions within the first array are organized in a plurality of multi-bit entries;
• said compare portion of each of said plurality of CAM cells is arranged a second array separate from said first array, such that a storage portion of the first CAM cell is disposed between a storage portion of said second CAM cell and a compare portion of the second CAM cell;
• and
• a plurality of bit buses each coupling a respective storage portion in the first array to a corresponding compare portion in the second array, such that the second array can concurrently compare all bits within the plurality of multi-bit entries of the first array with corresponding bits of a search vector.

A content addressable storage apparatus, comprising:

• a storage cell array including multiple storage cell entries that each include a plurality of storage cells that each store a single data bit, wherein said plurality of storage cells includes first and second storage cells;
• a plurality of match arrays physically separate from the storage cell array, wherein:
• each of said plurality of match arrays includes multiple compare cells that are each coupled to the plurality of storage cells within a respective one of said multiple storage cell entries;
• each compare cell includes compare circuitry that performs bit-wise comparison of bits from a search vector with data bits received from the plurality of storage cells within the associated storage cell entry;
• and
• said first storage cell is disposed between said second storage cell and said plurality of match arrays;
• and
• a plurality of bit buses each coupling a respective one of the plurality of storage cells in the storage cell array to a compare cell within each match array, such that the match arrays can concurrently compare all bits within each storage cell entry in the storage cell array with corresponding bits of a respective search vector.

A register renaming mapper for managing a register file of physical registers within an out-of-order processor, said register renaming mapper comprising:

• a memory array that stores data associating logical register names with physical registers within the register file;
• a memory content compare and match array coupled to the memory array to receive said data from the memory array and concurrently compare said data with multiple search vectors, wherein said memory content compare and match array outputs register identifiers identifying match relationships between physical registers and logical register names specified by said search vectors;
• a register allocation array coupled to the memory array that tracks allocation of the physical registers within the register file;
• an architected and replaced register array storing architected state information regarding said physical registers;
• and
• means for freeing physical registers and saving copies of register states.