Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus

A system for operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising:

• a data bus;
• a processor coupled to the data bus;
• a volatile memory coupled to the data bus;
• a non-volatile memory coupled to the data bus;
• a first control bus coupled to the volatile memory;
• a second control bus coupled to the non-volatile memory;
• and
• a multiplexed address bus coupled to the volatile memory and the non-volatile memory.

A system for operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising:

• a data bus;
• a processor coupled to the data bus;
• a volatile memory coupled to the data bus;
• a non-volatile memory coupled to the data bus;
• a bus master coupled to the data bus and the multiplexed address bus;
• and
• a multiplexed address bus coupled to the volatile memory and the non-volatile memory,
• wherein the bus master executes an access cycle to the volatile memory and concurrently precharges the non-volatile memory.

A system for operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising:

• a data bus;
• a processor coupled to the data bus;
• a volatile memory coupled to the data bus;
• a non-volatile memory coupled to the data bus;
• a bus master coupled to the data bus and the multiplexed address bus;
• and
• a multiplexed address bus coupled to the volatile memory and the non-volatile memory,
• wherein the bus master executes an access cycle to the non-volatile memory and concurrently precharges the volatile memory.

A method of operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising the steps of:

• providing first address information and first control information to the volatile memory;
• providing second address information and second control information to the non-volatile memory concurrent with providing first address and first control information to the volatile memory;
• performing a first data cycle over a data bus for the volatile memory corresponding to the first address and control information;
• and
• performing a second data cycle over the data bus for the non-volatile memory corresponding to the second address and control information after completion of the first data cycles,
• wherein the first data cycle is independent of the second data cycle.

A method of operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising the steps of:

• providing first address information and first control information to the non-volatile memory;
• providing second address information and second control information to the volatile memory concurrent with providing first address information and first control information to the non-volatile memory;
• performing a first data cycle over a data bus for the non-volatile memory corresponding to the first address and control information;
• and
• performing a second data cycle over the data bus for the volatile memory corresponding to the second address and control information after completion of the first data cycles,
• wherein the first data cycle is independent of the second data cycle.