Adder circuit and associated layout structure

An adder circuit which is formed using a plurality of n-type metal-oxide-semiconductor (NMOS) transistors and a plurality of p-type metal-oxide-semiconductor (PMOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,

• (a) said adder circuit including:
• a block carry propagation logic producing circuit for producing a block carry propagation logic, P0, for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said logic P0 at an output node;
• (b) said block carry propagation logic producing circuit including:
• a first block carry propagation logic producing section which is formed of said plurality of PMOS transistors and which has a logic that is expressed by the following equation:
• /P0=/gn+/pn·/gn−1+/pn·/pn−1·/gn−2 +/pn·/pn−1·/pn−2·/gn−3+/pn·/pn−1·/pn−2·/pn−3·/pn−4
• where the operator “/” designates logical inversion;
• and
• a second block carry propagation logic producing section which is formed of said plurality of NMOS transistors and which has a logic that is expressed by the following equation:
• P0=pn+gn·pn−1+gn·gn−1·pn−2 +gn·gn−1·gn−2·pn−3+gn·gn−1·gn−2·gn−3·pn−4.

An adder circuit which is formed using a plurality of n-type metal-oxide-semiconductor (NMOS) transistors and a plurality of p-type metal-oxide-semiconductor (PMOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,

• (a) said adder circuit including:
• a block carry generation logic producing circuit for producing a block carry generation logic, G0, for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said logic G0 at an output node;
• and
• a block carry propagation logic producing circuit for producing a block carry propagation logic, P0, for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together and for providing said logic P0 at said output node;
• wherein:
• a logic for producing said logic G0 in said block carry generation logic producing circuit is identical with a logic for producing said logic P0 in said block carry propagation logic producing circuit;
• said logic for producing said logic G0 is expressed by the following equations:
• GO=gn+pn·gn−1+pn·pn−1·gn−2 +pn·pn−1·pn−2·gn−3+pn·pn−1·pn−2·pn−3·gn−4
• /GO=/pn+/gn·/pn−1+/gn·/gn−1·/pn−2 +/gn·/gn−1·/gn−2·/pn−3+/gn·/gn−1·/gn−2·/gn−3·/gn−4
• where the operator “/” designates logic inversion;
• and
• said logic for producing said logic PO is expressed by the following equations:
• PO=gn+pn·gn−1+pn·pn−1·gn−2 +pn·pn−1·pn−2·gn−3+pn·pn−1·pn−2·pn−3·pn−4
• /PO=/pn+/gn·/pn−1+/gn·/gn−1·/pn−2 +/gn·/gn−1·/gn−2·/pn−3+/gn·/gn−1·/gn−2·/gn−3·/pn−4
• equal to or greater than two and for providing said logic G0 at an output node;
• and
• a block carry propagation logic producing circuit for producing a block carry propagation logic, P0, for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together and for providing said logic P0 at said output node;
• wherein:
• a logic for producing said logic G0 in said block carry generation logic producing circuit is identical with a logic for producing said logic P0 in said block carry propagation logic producing circuit;
• said logic for producing said logic G0 is expressed by the following equations:
• G0=gn+pn·gn−1+pn·pn−1·gn−2 +pn·pn−1·pn−2·gn−3+pn·pn−1·pn−2·pn−3·gn−4
• /G0=/pn+/gn·/pn−1+/gn·/gn−1·/pn−2 +/gn·/gn−1·/gn−2·/pn−3+/gn·/gn−1·/gn−2·/gn−3·/gn−4
• where the operator “/” designates logic inversion;
• and
• said logic for producing said logic PO is expressed by the following equations:
• P0=pn+gn·pn−1+gn·gn−1 pn−2 +gn·gn−1·gn−2·pn−3+gn·gn−1·gn−2·gn−3·pn−4
• /P0=/gn+/pn·/gn−1+/pn ·/pn−1·/gn−2 +/pn·/pn−1·/pn−2·/gn−3+/pn·/pn−1·/pn−2·/pn−3·/pn−4
• where the operator “/” designates logic inversion.

A layout structure for an adder circuit,

• said adder circuit which is formed using a plurality of metal-oxide-semiconductor (MOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,
• said adder circuit including:
• a block carry generation logic producing circuit for producing a block carry generation logic for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said block carry generation logic at an output node;
• said block carry generation logic producing circuit including:
• a single MOS transistor;
• and
• a plurality of series circuits, each of said plurality of series circuits being formed of m MOS transistors connected together in series where the number m is any integer ranging from two up to n+1;
• wherein:
• said single MOS transistor and said series circuits each have a terminal which is coupled to a supply voltage or to ground and another terminal which is coupled to said output node and together form a MOS transistor group in n+1 rows;
• and
• in two series circuits of said plurality of series circuits, one of which is formed of the greatest number of series-connected MOS transistors and the other of which is formed of the second largest number of series-connected MOS transistors, MOS transistors of said two series circuits whose drain regions are coupled to said output node share a drain region.

A layout structure for an adder circuit,

• said adder circuit which is formed using a plurality of metal-oxide-semiconductor (MOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,
• said adder circuit including:
• a block carry propagation logic producing circuit for producing a block carry propagation logic for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said block carry propagation logic at an output node;
• said block carry propagation logic producing circuit including:
• a single MOS transistor;
• and
• a plurality of series circuits, each of said plurality of series circuits being formed of m MOS transistors connected together in series where the number m is any integer ranging from two up to n+1;
• wherein:
• said single MOS transistor and said series circuits each have a terminal which is coupled to a supply voltage or to ground and another terminal which is coupled to said output node and together form a MOS transistor group in n+1 rows;
• in two series circuits of said plurality of series circuits, one of which is formed of the greatest number of series-connected MOS transistors and the other of which is formed of the second largest number of series-connected MOS transistors, MOS transistors of said two series circuits whose drain regions are coupled to said output node share a drain region.