Power saving method for performing additions and subtractions and a device thereof
AssigneeMotorola, Inc.
InventorsFabrice Aidan, Yoram Salant, Mark Elnekave, Leonid Tsukerman
Life of this patent
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Abstract
A power saving device and method for either adding or subtracting a constant from an operand, by checking a logic value of a portion of the operand and deciding whether to activate a multi-bit adder or to perform the subtraction or addition by inverting a portion of the operand. The power saving device and method is especially efficient when the constant K equals 2n. Then, the n'th bit of the operand is checked and if the addition or subtraction operation can be performed by inverting the n'th bit of the operand, a result is generated by that inversion, while a multi-bit adder is disabled.
Claims10
A power saving adding and subtracting unit for adding and subtracting a constant from an operand, the power saving adding and subtracting unit is adapted to receive the operand and the constant and perform a selected operation out of adding operation and subtracting operation, the power saving adding and subtracting unit comprising:
- a detect and invert logic, for receiving a first portion of the operand;
- checking whether the selected operation can be performed by inverting at least one bit of the first portion of the operand, responsive to the constant;
- wherein if the answer is YES, disabling the multi-bit adder and subtractor and generating a first portion of a result by inverting at least one bit of the portion of the operand, responsive to the constant;
- a multi-bit adder and subtractor unit for generating a second result by performing the selected operation;
- and
- a selection means for selecting the second result when the adder and subtractor is enabled, and for selecting a first result comprising from a second portion of the operand that was not sent to the detect and invert logic and the first portion of the first result when the selected operation is performed by inverting at least one bit of the first portion of the operand responsive to the constant.
A power saving method for performing a selected operation out of adding a constant to an operand and subtracting the constant of the operand, the operand is comprised of a first portion and a second portion, the method comprising the steps of:
- receiving the operand, checking the first portion of the operand and determining whether the selected operation can be performed by inverting at least one bit of the first portion, responsive to the constant;
- if the answer is YES jumping to a step for generating a result by inverting at least one bit of the first portion, responsive to the constant;
- if the answer is NO jumping to a step for generating a result by a multi-bit adder and subtractor;
- generating a first portion of a result by inverting at least one bit of the first portion, responsive to the constant, providing a result comprising of the second portion of the operand and of the first portion of the result and jumping to the step of receiving the operand;
- enabling a multi-bit adder and subtractor unit and generating a result by the multi-bit adder and subtractor;
- disabling the adder and subtractor unit and jumping to the step of receiving the operand.
Dependencies are inferred from the claim text.