Floating-point and integer multiply-add and multiply-accumulate
AssigneeSandCraft, Inc.
InventorJack H. Choquette
Life of this patent
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Abstract
A method and a device including, in one embodiment, a multiply array and at least one adder to perform a floating-point multiplication followed by an addition when operands are in floating-point format. The device is also configured to perform an integer multiplication followed by an accumulation when operands are in integer format. The device is further configured to perform a floating-point multiply-add or an integer multiply-accumulation in response to control signals. In another embodiment, the device contains an adder and the adder is capable of performing a floating-point addition and an integer accumulation. The adder is configured to be extra wide to reduce operand misalignment. Moreover, the device stalls the process in response to operand misalignment.
Claims20
A multiply-accumulate (MACC) circuit comprising:
- a multiply array to perform floating point and integer multiplication;
- a first adder coupled to the multiply array to perform floating point and integer addition;
- a shifter coupled to the first adder;
- a second adder coupled to the shifter to perform floating point and integer addition and accumulation, wherein a precision of the second adder is greater than a precision of the multiply array, and a precision of the first adder;
- a first bypass coupling an output of the second adder to an input of the second adder;
- a second bypass coupling an output of the second adder to an input of the shifter;
- wherein the first bypass is shorter than the second bypass.
A method of operating a multiply-accumulate (MACC) circuit comprising:
- obtaining a multiplication result by multiplying a first operand and a second operand, wherein the first and second operands may be represented in integer or floating point formats;
- determining whether the multiplication result can be aligned with a first result in an adder, wherein the first result is in floating point format and the precision of the first result is greater than the precision of the multiplication result;
- based, at least in part on the determination, either aligning the multiplication result with the first result in the adder, or aligning the first result in the adder with the multiplication result.
A computer readable medium containing instruction thereon, which when executed by a processor cause the processor to operate a multiply-accumulate (MACC) circuit by:
- obtaining a multiplication result by multiplying a first operand and a second operand, wherein the first and second operands may be represented in integer or floating point formats;
- determining whether the multiplication result can be aligned with a first result in an adder, wherein the first result is in floating point format and the precision of the first result is greater than the precision of the multiplication result;
- based, at least in part on the determination, either aligning the multiplication result with the first result in the adder, or aligning the first result in the adder with the multiplication result.
A computer comprising:
- a multiply-accumulate (MACC) circuit, wherein the MACC circuit comprises:
- a multiply array to perform floating point and integer multiplication;
- a first adder coupled to the multiply array to perform floating point and integer addition;
- a shifter coupled to the first adder;
- a second adder coupled to the shifter to perform floating point and integer addition and accumulation, wherein a precision of the second adder is greater than a precision of the multiply array, and a precision of the first adder;
- a first bypass coupling an output of the second adder to an input of the second adder;
- a second bypass coupling an output of the second adder to an input of the shifter;
- wherein the first bypass is shorter than the second bypass.
Dependencies are inferred from the claim text.