US 6,480,869 B1Granted

Random-number generating circuit, non-contact IC card having random-number generating circuit, reader/writer, and method of testing an apparatus having the random generating circuit

AssigneesMitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation

InventorShuzo Fujioka

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Abstract

A random-number generating circuit comprising a plurality of shift registers synchronized with a clock and cascaded together, a circuit that obtains the sum of the outputs of more than one of the shift registers and inputs the obtained sum to the input terminal of the shift register on the first level, and a clock generating circuit that inputs a clock signal to each of the shift registers. One or more of the shift registers have external-signal input terminals and an addition circuit that adds bit data input through the external-signal input terminals to bit data of one or more of the bits stored within. The random-number generating circuit outputs as random-number data the bit data obtained from the addition by the addition circuit.

Claims6

Dependent claims

A random-number generating circuit comprising:

a plurality of shift registers of clock synchronization type being cascaded so as to generate a random-number of predetermined bit number with parallel outputs of said plurality of shift registers;
a circuit that obtains a sum of serial outputs of two or more of said plurality of shift registers to input the obtained sum to an input terminal of the first stage shift register;
a clock generating circuit that generates a clock signal to input the clock signal to each shift register;
an external data input means that inputs external bit data of a predetermined number of bits to one or more of said plurality of shift registers;
and
a plurality of adders arranged within one or more of said plurality of shift registers, each adder adding corresponding one bit of the input external bit data to corresponding one bit of bit data being shifted within corresponding shift register, thereby the random-number including a plurality of bit data added by said plurality of adders, and wherein each shift register is comprised of one or more flip-flop circuits of clock synchronization type the number of which is equal to the number of parallel output bits of each shift register, and wherein each flip-flop circuit provides with a first element for making an output data HIGH upon turning an electric power on and a second element for making an output data LOW upon turning the electric power on, said second element having a derivability same to that of said first element.

3 more elements

A random-number generating circuit comprising:

a plurality of shift registers of clock synchronization type being cascaded so as to generate a random-number of predetermined bit number with parallel outputs of said plurality of shift registers;
a circuit that obtains a sum of serial outputs of two or more of said plurality of shift registers to input the obtained sum to an input terminal of the first stage shift register;
and
a clock generating circuit that generates a clock signal to input the clock signal to each shift register,
said clock generating circuit having a clock circuit that generates a clock signal of a predetermined frequency and a phase-locked loop circuit that receives the clock signal generated by said clock circuit as a reference frequency signal and output a clock signal to each of said plurality of shift registers, and wherein each shift register is comprised of one or more flip-flop circuits of clock synchronization type the number of which is equal to the number of parallel output bits of each shift register, and wherein each flip-flop circuit provides with a first element for making an output data HIGH upon turning an electric power on and a second element for making an output data LOW upon turning the electric power on, said second element having a derivability same to that of said first element.

2 more elements

A non-contract IC card for communicating information with a reader/writer, said non-contact IC card having:

a built-in random-number generating circuit that comprises
a plurality of shift registers of clock synchronization type being cascaded so as to generate a random-number of predetermined bit number with parallel outputs of said plurality of shift registers;
a circuit that obtains a sum of serial outputs of two or more of said plurality of shift registers to input the obtained sum to an input terminal of the first stage shift register;
a clock generating circuit that generates a clock signal to input the clock signal to each shift register;
an external data input means that inputs external bit data of a predetermined number of bits to one or more of said plurality of shift registers;
and
a plurality of adders arranged within one or more of said plurality of shift registers, each adder adding corresponding one bit of the input external bit data to corresponding one bit of bit data being shifted within corresponding shift register, thereby the random-number including a plurality of bit data added by said plurality of adders;
and
wherein each shift register is comprised of one or more flip-flop circuits of clock synchronization type the number of which is equal to the number of parallel output bits of each shift register, and wherein each flip-flop circuit provides with a first element for making an output data HIGH upon turning an electric power on and a second element for making an output data LOW upon turning the electric power on, said second element having a derivability same to that of said first element;
and
a control circuit that performs communication with said reader/writer using a random-number generated by said built-in random-number generating circuit;
and
wherein said external data input means is connected to a signal line connected to said control circuit to fetch bit data carried on said signal line into one or more of said plurality of shift registers.

10 more elements

Dependencies are inferred from the claim text.