CDMA demodulating method and demodulator

A code division multiple access (CDMA) demodulating method performed in a CDMA system, comprising the steps of:

• (a) sequentially-storing all input data, which are over-sampled by M-fold and go through a number (N) of paths, in a predetermined first memory, where M and N are predetermined positive integers;
• (b) generating PN codes for each of the N paths;
• (c) storing the PN codes in a predetermined second memory;
• (d) complex-conjugating the PN codes;
• (e) checking whether traffic walsh codes of all one period are stored in a predetermined third memory;
• (f) sequentially-storing the traffic walsh codes by generating the traffic walsh codes, which correspond to a first access path, until traffic walsh codes of all one period, which corresponds to a processing gain L, are stored in a case where traffic walsh codes of all one period are not stored in the third memory;
• (g) omitting the performance of the step (f) in a case where traffic walsh codes of all one period are stored in the third memory;
• (h) multiplying a complex-conjugated value with one of the values stored in the second memory and one of the values stored in the first memory;
• (i) performing a control operation for storing the PN codes in a predetermined address of the second memory and a control operation for outputting data for each of the N paths from the first, second, and third memories;
• (j) multiplying the resultant value of the step (h) with the traffic walsh codes of a corresponding path of data stored in the third memory;
• (k) cumulatively summing the resultant value of the step (j) L times for each of the N multi-paths to be processed, where L corresponds to the processing gain;
• (l) cumulatively summing the resultant value of the step (h) X times for each of the multi-paths to be processed, where X corresponds to the data bit number of the walsh codes;
• (m) checking whether L-1 resultant values are accumulated;
• (n) checking whether N resultant values are accumulated when it is determined that the L-1 resultant values are not accumulated in the step (m);
• (o) repeatedly-performing the steps (j) through (n) with respect to the values by outputting the values, which correspond to a next path in the first, second, third memories when it is determined that the N resultant values are not accumulated in the step (n);
• (p) performing the steps (a) through (o) when it is determined that work with respect to the N-th path is completed in the step (n);
• (q) performing the steps (a) through (l) when it is determined that the L-1 resultant values are accumulated in the step (m);
• (r) multiplying the complex-conjugated values of the resultant value of the step (l) with the resultant value of the step (k);
• (s) sequentially-obtaining a number (N) of values by sequentially-inputting the number (N) of data obtained in the step (r) and taking only real values;
• (t) cumulatively summing the data obtained in the step (s) N times;
• and
• (u) deciding bit values based on logic values identified by identifying the logic values of the result of the step (t).

A code division multiple access (CDMA) demodulator used in a CDMA system, comprising:

• a first memory for sequentially-storing input data, which are over-sampled by M-fold, where M is a predetermined positive integer;
• a PN codes-generating unit for generating different PN codes for each path;
• a second memory for sequentially-storing the PN codes output from the PN codes-generating unit;
• a first complex-conjugating unit for complex-conjugating the PN codes by inputting from the second memory the PN codes generated by the PN codes-generating unit;
• a first multiplying unit for multiplying a complex-conjugated value of one of the values stored in the second memory with one of values stored in the first memory;
• a controlling unit for performing a control operation for storing the PN codes generated in the PN codes-generating unit in the same address as the modulo K-operated result, in the order in which the PN codes are received from the second memory and for performing a control operation for outputting data for each path from the first, second, and third memories;
• a second multiplying unit for multiplying a value output from the first multiplying unit with the traffic walsh codes of a corresponding path of data stored in the third memory;
• a N-path L-accumulating unit for cumulatively-summing the output data of the second multiplying unit L times for each of the N multi-paths to be processed, where L corresponds to the processing gain;
• a N-path X-accumulating unit for cumulatively-summing the data output from the first multiplying unit X times for each of the N multi-paths to be processed, where X corresponds to the data bit number of the walsh codes;
• a second complex-conjugating unit for complex-conjugating the output values of the N-path X-accumulating unit by inputting the output values of the N-path X-accumulating unit;
• a third multiplying unit for multiplying the output values of the second complex-conjugating unit with the output values of the N-path L-accumulating unit;
• a real-values extracting unit for sequentially and for each path independently inputting N data values output from the third multiplying unit, and for sequentially-outputting the N independent values for each path, and taking only real values;
• an accumulating unit for cumulatively-summing the data sequentially-output from the real-values sampling unit N times;
• and
• a bit-deciding unit for deciding bit values based on logic values identified by identifying the logic values of the output of the accumulating unit.