High speed network switch bus clock
AssigneeNational Semiconductor Corporation
InventorsBrian Gaudet, Vickie Pagnon
Life of this patent
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Abstract
A high-speed network switch includes a data bus for transmitting data between devices. The data bus includes a plurality of data lines and a clock line. As packet data is received by the high-speed network switch, the packet data is divided into byte-wide cells for transmission over the data lines. While the cells are transmitted over the data lines, a half-speed clock is transmitted over the clock line. Transitions in the half-speed clock occur during transmission of the cell data. The transitions are used by a receiving device to sample the byte-wide cells.
Claims38
A network device configured to convey data between a bus and a port, the network device comprising:
- a plurality of data paths configured to receive data signals at a bit rate from other network devices;
- a clock path configured to receive a clock signal at a fraction of the bit rate from the other network devices;
- and
- a memory operationally coupled with the plurality of data lines and the clock line and having a first portion and a second portion wherein the memory is configured to receive one byte of data into the first portion after a first transition in the clock signal and to receive another byte of data into the second portion after a second transition in the clock signal.
A method of transmitting packet data over a bus comprising the steps of:
- transmitting a first data signal over a data bus at a bit rate;
- transmitting a clock signal over a clock line at a fraction of the bit rate wherein the clock signal passes through a first transition during transmission of the first data signal;
- and
- transmitting a second data signal over the data bus wherein the clock signal passes through a second transition during transmission of the second data signal.
A method of transmitting packet data over a bus comprising the steps of:
- transmitting a first data signal over a data bus at a bit rate;
- transmitting a clock signal over a clock line at a fraction of the bit rate wherein the clock signal passes through a first transition during transmission of the first data signal;
- transmitting a second data signal over the data bus wherein the clock signal passes through a second transition during transmission of the second data signal;
- receiving packet data via a port;
- and
- dividing the packet data into a plurality of cells, and wherein in the step of transmitting a first data signal, the first data signal comprises a first one of the plurality of cells.
A method of receiving packet data over a bus comprising the steps of:
- receiving a first data signal at a bit rate over a bus;
- receiving a second data signal at the bit rate over the bus;
- receiving a clock signal at a fraction of the bit rate over the bus;
- sampling the first data signal during a first transition in the clock signal;
- and
- sampling the second data signal during a second transition in the clock signal, wherein the second transition occurs immediately following the first transition.
A data bus driver comprising:
- a bus having n data lines and a clock line;
- and
- a device connected to the bus, the device transmitting a series of n-bit data words onto the data lines, the n-bit data words including a first n-bit data word of the series and a second n-bit data word of the series, the device transmitting a clock signal having a series of edges onto the clock line, the edges including a first edge of the series of edges that transition from a first voltage level to a second voltage level and a second edge of the series of edges that transition from the second voltage level to the first voltage level, the device transmitting the first n-bit data word onto the data lines so that only the first edge occurs during the transmission of the first n-bit data word, and transmitting the second n-bit data word onto the data lines so that only the second edge occurs during the transmission of the second n-bit data word.
A data bus system comprising:
- a bus having n data lines and a clock line;
- and
- a plurality of devices connected to the bus, each device transmitting a series of n-bit data words onto the data lines at different times, the n-bit data words including a first n-bit data word of the series and a second n-bit data word of the series, the device transmitting a clock signal having a series of edges onto the clock line, the edges including a first edge of the series of edges that transitions from a first voltage level to a second voltage level and a second edge of the series of edges that transitions from the second voltage level to the first voltage level, the device transmitting the first n-bit data word onto the data lines so that only the first edge occurs during the transmission of the first n-bit data word, and transmitting the second n-bit data word onto the data lines so that only the second edge occurs during the transmission of the second n-bit data word.
A method of transmitting a series of n-bit data words and a clock signal onto a bus having n data lines and a clock line from a device connected to the bus, the n-bit data words including a first n-bit data word of the series and a second n-bit data word of the series, the clock signal having a series of edges, the edges including a first edge of the series of edges that transitions from a first voltage level to a second voltage level and a second edge of the series of edges that transitions from the second voltage level to the first voltage level, the method comprising the steps of:
- transmitting the first n-bit data word onto the data lines and the clock signal onto the clock line from the device so that only the first edge occurs during the transmission of the first n-bit data word, and
- transmitting the second n-bit data word onto the data lines and the clock signal onto the clock line from the device so that only the second edge occurs during the transmission of the second n-bit data word.
A data bus for transmitting data between a plurality of devices, comprising:
- a plurality of data lines configured to connect with a plurality of devices and to convey data signals at a bit rate between the plurality of devices;
- and
- a clock line configured to connect with the plurality of devices and to convey a clock signal at a fraction of the bit rate between the plurality of devices, and
- wherein the plurality of data lines and the clock line are further configured to receive the data signals and the clock signal, respectively, from any one of the plurality of devices, and
- wherein clock signal transitions occur during an assertion state of the data signals, and wherein the clock signal transitions are substantially centered on the assertion state of the data signals, and wherein a positive transition in the clock signal occurs during data signals of one byte and a negative transition in the clock signal occurs during data signals of another byte.
Dependencies are inferred from the claim text.