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US 6,480,435 B2Granted
Semiconductor memory device with controllable operation timing of sense amplifier
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYayoi Nakamura, Takashi Itou
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Abstract
A semiconductor memory device includes control circuits for respectively controlling operation timings of respective sense amplifiers related to an odd-numbered bit line pair and related to an even-numbered bit line pair. The control circuits thus allow respective sense amplifiers provided for bit line pairs adjacent to each other to operate at different timings respectively.
Claims14
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines arranged corresponding to respective rows, and a plurality of bit line pairs arranged corresponding to respective columns;
- first sense amplifiers for detecting potential differences of a first plurality of even-numbered bit line pairs among said plurality of bit line pairs;
- second sense amplifiers for detecting potential differences of a second plurality of odd-numbered bit line pairs among said plurality of bit line pairs;
- and
- a sense amplifier control circuit for individually controlling respective operation timings of said first and second sense amplifiers.
2 more elements
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines arranged corresponding to respective rows, and a plurality of bit line pairs arranged corresponding to respective columns;
- first sense amplifiers for detecting potential differences of a first plurality of even-numbered bit line pairs among said plurality of bit line pairs;
- second sense amplifiers for detecting potential differences of a second plurality of odd-numbered bit line pairs among said plurality of bit line pairs;
- a first line supplying voltage for precharging said first plurality of even-numbered bit line pairs;
- a second line supplying voltage for precharging said second plurality of odd-numbered bit line pairs;
- and
- a control circuit for individually controlling respective voltages of said first and second lines.
4 more elements
Dependencies are inferred from the claim text.