Memory device with precharge reinforcement circuit
AssigneeHynix Semiconductor Inc.
InventorIhl-Ho Lee
Life of this patent
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Abstract
A memory device includes: a plurality of cell array blocks provided with a plurality of memory cells coupled to a word line and a bit line pair; a bit line control block including a first control block and a second control block, wherein the first control block is separately coupled to a first bit line pair coupled to a first cell array block among the cell array blocks, and the second control block is shared with a second bit line pair commonly coupled to the first cell array block and a second cell array block adjacent to the first cell array block; and a precharge reinforcement unit, coupled to a predetermined portion of the first control block, for reducing a precharge speed difference between the first bit line pair and the second bit line pair.
Claims13
A memory device comprising:
- a plurality of cell array blocks provided with a plurality of memory cells coupled to a word line and a bit line pair;
- a bit line control block including a first control block and a second control block, wherein the first control block is separately coupled to a first bit line pair coupled to a first cell array block among the cell array blocks, and the second control block is shared with a second bit line pair commonly coupled to the first cell array block and a second cell array block adjacent to the first cell array block;
- and
- precharge reinforcement means, coupled to a predetermined portion of the first control block, for reducing a precharge speed difference between the first bit line pair and the second bit line pair.
A memory device comprising:
- a plurality of cell array blocks provided with a plurality of memory cells coupled to a word line and a bit line pair;
- a bit line control block including a first control block and a second control block, wherein the first control block is separately coupled to a first bit line pair coupled to a first cell array block among the cell array blocks, and the second control block is shared with the first bit line pair commonly coupled to the first cell array block and a second cell array block adjacent to the first cell array block;
- a precharge voltage applying terminal for providing a precharge voltage to the first bit line pair;
- equalization reinforcement means for equalizing the first bit line pair to the precharge voltage level provided from the precharge voltage applying terminal;
- and
- precharge reinforcement means, coupled between the equalization reinforcement means and the first control block, for reducing a precharge speed difference between the first bit line pair and the second bit line pair.
Dependencies are inferred from the claim text.