Back to results
US 6,480,433 B2Granted
Dynamic random access memory with differential signal on-chip test capability
AssigneeTexas Instruments Incorporated
InventorJames D. Huffman
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeTexas Instruments Incorporated
InventorJames D. Huffman
Estimating the term…
A differential amplifier circuit used to test the underlying DRAM memory cells in large area spatial light modulator (SLM) arrays by significantly increasing the cell capacitance to bitline capacitance ratio. Since for these SLM devices it is not desirable to sub-divide the DRAM array into smaller test arrays in order to reduce the bitline capacitance, this invention addresses the bitline capacitance problem by reading the differential voltage between two adjacent cells rather than the actual voltage of each cell. The approach is to load, precharge, and readout a checkerboard pattern and then repeat the process for an inverse checkerboard pattern. Cell outputs which have the same value for the two complimentary patterns indicate a cell failure. In this approach, the cell differential voltage readout is effectively doubled to approximately ±200 mVolts, providing 100% test coverage of these large area arrays. This results in an effective DRAM test procedure which is independent of bitline capacitance.
A method for testing an unsegmented large area DRAM array, comprising:
In an integrated circuit having an unsegmented large area DRAM array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged in rows and columns, each memory cell including a memory cell and a select transistor, the select transistor having a conduction path connected to its storage capacitor and to a bit line of its associated column, and having a control electrode connected to a word line of its associated row, a circuit for testing the DRAM array comprising:
Dependencies are inferred from the claim text.