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US 6,480,432 B1Granted
Flash memory device having mask ROM cells for self-test
AssigneeFujitsu Limited
InventorTomohiro Nakayama
Life of this patent
Estimating the term…
Abstract
Memory cell blocks 10 to 17 are respectively provided with mask ROM cell rows and different values from one another are respectively stored in the mask ROM cell rows. A mask ROM cell row selecting circuit 5i makes transfer gates of mask ROM cells in a memory cell block 1i corresponding to a block selection signal BSi turned on when a test mode signal *TM and the block selection signal BSi are both active wherein i=1 to 7. A word line selection signal is made inactive when the test mode signal *TM is active. Tests on short between address signal lines and other defects are effected in a procedure wherein a test mode is activated, block selection signals are sequentially activated to read contents of mask ROM cell rows and the contents are compared with expected values.
Claims11
A flash memory device comprising:
- a memory cell array having a plurality of memory cell blocks, each memory cell block having cells arranged in rows and columns, each row including a word line coupled to a plurality of EPROM cells, each column including a bit line coupled to a plurality of EPROM cells, one of said memory cell blocks being selected by block selection signals, contents of EEPROM cells coupled to a selected word line being read on respective bit lines;
- a mask ROM cell array having a plurality of mask ROM cell rows and a plurality of mask ROM cell columns, each mask ROM cell row arranged in each memory cell block, different mask ROM cell rows having different contents to each other, each mask ROM cell column having transfer gates coupled to a bit line, each mask ROM cell row including a word line coupled to said transfer gates;
- a mask ROM cell row selecting circuit, arranged for each mask ROM cell row, for making said transfer gates, which are in said memory cell block corresponding to an activated one of said block selection signals, on-state when a test mode signal is active;
- and
- a word decoder, arranged for each memory cell block, for activating one of said word lines in response to input signals of predecoded address when said test mode signal is inactive and corresponding block selection signal is active and for inactivating all said word lines when said test mode signal is active.
2 more elements
A test method for a flash memory device, comprising the steps of:
- preparing said flash memory device which comprises:
- a memory cell array having a plurality of memory cell blocks, each memory cell block having cells arranged in rows and columns, each row including a word line coupled to a plurality of EPROM cells, each column including a bit line coupled to a plurality of EPROM cells, one of said memory cell blocks being selected by block selection signals, contents of EEPROM cells coupled to a selected word line being read on respective bit lines;
- a mask ROM cell array having a plurality of mask ROM cell rows and a plurality of mask ROM cell columns, each mask ROM cell row arranged in each memory cell block, different mask ROM cell rows having different contents to each other, each mask ROM cell column having transfer gates coupled to a bit line, each mask ROM cell row including a word line coupled to said transfer gates;
- a mask ROM cell row selecting circuit, arranged for each mask ROM cell row, for making said transfer gates in said memory cell block corresponding to an activated one of said block selection signals on-state when a test mode signal is active;
- and
- a word decoder, arranged for each memory cell block, for activating one of said word lines in response to input signals of predecoded address when said test mode signal is inactive and corresponding block selection signal is active and for inactivating all said word lines when said test mode signal is active,
- activating said test mode signal;
- reading contents of selected one of said mask ROM cell rows with changing a state of said block selection signals;
- comparing said contents with a corresponding expected value;
- and
- judging that said flash memory device is defective when said contents and said expected value do not coincide with each other.
8 more elements
A flash memory device comprising:
- a memory cell array having a plurality of memory cell blocks, each memory cell block having cells arranged in rows and columns, each row including a word line coupled to a plurality of EPROM cells, each column including a bit line coupled to a plurality of EPROM cells, one of said memory cell blocks being selected by block selection signals, contents of EEPROM cells coupled to a selected word line being read on respective bit lines;
- a mask ROM cell array having a plurality of mask ROM cell rows and a plurality of mask ROM cell columns, each mask ROM cell row arranged in each memory cell block, different mask ROM cell rows having different contents to each other, each mask ROM cell column having transfer gates coupled to a bit line, each mask ROM cell row including a word line coupled to said transfer gates;
- a mask ROM cell row selecting circuit, arranged for each mask ROM cell row, for making said transfer gates, which are in said memory cell block corresponding to an activated one of said block selection signals, on-state when a test mode signal is active;
- and
- a word decoder, arranged for each memory cell block, for inactivating all said word lines when said test mode signal is active.
2 more elements
Dependencies are inferred from the claim text.