Semiconductor having mechanism capable of operating at high speed

A semiconductor memory device, comprising:

• a plurality of normal blocks including a plurality of normal memory cells and a plurality of bit lines;
• a spare memory block including a plurality of spare memory cells and a plurality of bit lines for replacing and repairing a defective normal memory cell in a corresponding normal block;
• select means responsive to an external address signal for selecting a corresponding normal block and a corresponding spare block;
• spare determining means responsive to an external address signal for determining whether or not to carry out said replacing and repairing using said spare block;
• a plurality of sense amplifier blocks arranged to correspond to said plurality of normal blocks and said spare block and including a plurality of sense amplifiers each operative in response to a sense amplifier activation signal to read/write data from/to a corresponding bit;
• and
• a plurality of bit line potential drive means arranged to correspond to said plurality of sense amplifiers, each of said plurality of bit line potential drive means including a capacitive element for use in an active cycle to pull up a potential of said corresponding bit line.