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US 6,480,429 B2Granted
Shared redundancy for memory having column addressing
AssigneeMicron Technology, Inc.
InventorsWilliam F. Jones, Wen Li
Life of this patent
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Abstract
A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.
Claims36
A shared redundancy memory circuit comprising:
- a main memory portion comprising a plurality of addresses, each of the plurality of addresses comprising a plurality of address bits and each of the plurality of addresses corresponding to a first memory segment and a second memory segment;
- a redundant memory portion configured to replace one or more addresses in the main memory portion;
- a plurality of state devices, each of the plurality of state devices corresponding to one of the plurality of address bits and configured to provide access to the redundant memory portion through the plurality of addresses corresponding to the first memory segment and the second memory segment, and wherein the first and second bits of the plurality of address bits from the first memory segment are compared to the corresponding first and second state devices using a first exclusive NOR gate to produce a first memory segment output for each of the first and second address bits;
- and
- a plurality of logical devices configured to detect the state of each of the plurality of redundancy fuses corresponding to each of the plurality of address bits.
2 more elements
A method of prefetching data from a memory device comprising the acts of:
- (a) receiving a first address bit from a first segment of the memory device, the first address bit comprising one bit of a corresponding first address;
- (b) receiving a second address bit from a second segment of the memory device;
- (c) comparing the first address bit to a state of a first fuse using a first exclusive NOR (XNOR) gate to determine if the state of the first fuse matches the first address bit;
- and
- (d) comparing the second address bit to the state of the first fuse to determine if the state of the first fuse matches the second address bit.
2 more elements
A method of prefetching data from a memory device comprising the acts of:
- (a) receiving a first address bit from a first segment of the memory device, the first address bit comprising one bit of a corresponding first address;
- (b) receiving a second address bit from a second segment of the memory device, the second address bit comprising one bit of a corresponding second address;
- (c) receiving a third address bit from the first segment of the memory device, the third address bit corresponding to the second address;
- (d) comparing the first address bit to a state of a fuse using a first exclusive NOR (XNOR) gate to determine if the state of the first fuse matches the first address bit;
- (e) comparing the second address bit to the state of the fuse to determine if the state of the second fuse matches the second address bit;
- and
- (f) comparing the third address bit to the state of the fuse to determine if the state of the second fuse matches the third address bit.
4 more elements
A method of accessing a memory array comprising the acts of:
- (a) providing a first address corresponding to a first segment on one of the rising edge and the falling edge of a clock cycle;
- (b) providing a second address corresponding to a second segment on the other of the rising and the falling edge of the clock cycle;
- (c) comparing a first bit of the first address to a first fuse using a first XNOR gate to produce a first output corresponding to the first segment;
- (d) comparing a second bit of the first address to a second fuse using the first XNOR gate to produce a second output corresponding to the first segment;
- (e) comparing a first bit of the second address to the first fuse using a second XNOR gate to produce a third output corresponding to the second segment;
- and
- (f) comparing a second bit of the second address to the second fuse using the second XNOR gate to produce a fourth output corresponding to the second segment.
4 more elements
A method of prefetching data from a memory device comprising the acts of:
- (a) receiving a first address bit from a first segment of the memory device, the first address bit comprising one bit of a corresponding first address;
- (b) receiving a second address bit from a second segment of the memory device;
- (c) comparing the first address bit to a state of a first fuse to determine if the state of the first fuse matches the first address bit;
- and
- (d) comparing the second address bit to the state of the first fuse using a first exclusive NOR (XNOR) gate to determine if the state of the first fuse matches the second address bit.
2 more elements
A method of prefetching data from a memory device comprising the acts of:
- (a) receiving a first address bit from a first segment of the memory device, the first address bit comprising one bit of a corresponding first address;
- (b) receiving a second address bit from a second segment of the memory device, the second address bit comprising one bit of a corresponding second address;
- (c) receiving a third address bit from the first segment of the memory device, the t third address bit corresponding to the second address;
- (d) comparing the first address bit to a state of a fuse to determine if the state of the first fuse matches the first address bit;
- (e) comparing the second address bit to the state of the fuse using a first exclusive NOR (XNOR) gate to determine if the state of the second fuse matches the second address bit;
- and
- (f) comparing the third address bit to the state of the fuse to determine if the state of the second fuse matches the third address bit.
4 more elements
A method of prefetching data from a memory device comprising the acts of:
- (a) receiving a first address bit from a first segment of the memory device, the first address bit comprising one bit of a corresponding first address;
- (b) receiving a second address bit from a second segment of the memory device, the s second address bit comprising one bit of a corresponding second address;
- (c) receiving a third address bit from the first segment of the memory device, the third address bit corresponding to the second address;
- (d) comparing the first address bit to a state of a fuse to determine if the state of the first fuse matches the first address bit;
- (e) comparing the second address bit to the state of the fuse to determine if the state of the second fuse matches the second address bit;
- and
- (f) comparing the third address bit to the state of the fuse using a first exclusive NOR (XNOR) gate to determine if the state of the second fuse matches the third address bit.
4 more elements
Dependencies are inferred from the claim text.