High-speed cycle clock-synchronous memory device

A semiconductor memory device comprising:

• a plurality of memory cells divided into a plurality of physical cell arrays defined by a physical structure of the memory cells and divided into a plurality of logical cell arrays, each of said logical cell arrays being treated as an independent access unit by a memory controller;
• wherein a relationship between said physical cell arrays and said logical cell arrays depends on a replacement of defective word lines in said physical cell arrays.

A semiconductor memory device comprising:

• a plurality of memory cells divided into a plurality of physical cell arrays defined by a physical structure of the memory cells and divided into a plurality of logical cell arrays, each of said logical cell arrays being accessed as an independent access unit;
• wherein a relationship between said physical cell arrays and said logical cell arrays depends on a replacement of defective word lines in said physical cell arrays.

A semiconductor memory device comprising:

• a plurality of memory cells divided into a plurality of physical cell arrays defined by a physical structure of the memory cells and divided into a plurality of logical cell arrays, each of said logical cell arrays being treated as an independent access unit by a memory controller;
• wherein said logical cell arrays where spare word lines can be replaced can be varied in size by address setting depending on a utilization rate of redundancy.

A semiconductor memory device comprising:

• a plurality of memory cells divided into a plurality of physical cell arrays defined by a physical structure of the memory cells and divided into a plurality of logical cell arrays, each of said logical cell arrays being accessed as an independent access unit;
• wherein said logical cell arrays where spare word lines can be replaced can be varied in size by address setting depending on a utilization rate of redundancy.

A memory system comprising:

• a memory controller;
• a plurality of memory cells divided into a plurality of physical cell arrays which is defined by a physical structure of the memory cells and divided into a plurality of logical cell arrays, said memory controller treating each of said logical cell arrays as an independent access unit;
• wherein a relationship between said physical cell arrays and said logical cell arrays depends on a replacement of defective word lines in said physical cell arrays.

A memory system comprising:

• a memory controller;
• a plurality of memory cells divided into a plurality of physical cell arrays which is defined by a physical structure of the memory cells and divided into a plurality of logical cell arrays, said memory controller treating each of said logical cell arrays as an independent access unit;
• wherein said logical cell arrays where spare word lines can be replaced can be varied in size by address setting depending on utilization rate of redundancy.