Semiconductor non-volatile storage

A non-volatile semiconductor storage, comprising:

• a plurality of main bit lines including first and second main bit lines;
• a plurality of sub bit lines including first and second sub bit lines;
• a differential sense amplifier connected to said first and second main bit lines;
• a first transistor disposed between said first main bit line and said first sub bit line;
• a second transistor disposed between said second main bit line and said second sub bit line;
• a plurality of word lines including first and second word lines;
• a common source line;
• a plurality of first memory cells each comprising a control gate, a drain terminal and a source terminal, wherein said control gate of said first memory cell is connected to said first word lines, said drain terminal of said first memory cell is connected to said first sub bit line and said source terminal of said first memory cell is connected to said common source line;
• and
• a plurality of second memory cells each comprising a control gate, a drain terminal and a source terminal, wherein said control gate of said second memory cell is connected to said second word line, said drain terminal of said second memory cell is connected to said second sub bit line and said source terminal of said second memory cell is connected to said common source line;
• wherein, when gate signals of said first and second transistors are activated, said first main bit line is a read bit line and said second main bit line is reference bit line, for reading a memory cell which is one of said first memory cells,
• wherein said differential sense amplifier executes a reading method characterized in that a current which is about ½ current of a memory cell current is applied only to said read bit line in a direction opposing said memory cell current while or after said read bit line and said reference bit line are pre-charged.