Global/local memory decode with independent program and read paths and shared local decode
AssigneeIntel Corporation
InventorDaniel R. Elmhurst
Life of this patent
Estimating the term…
Abstract
A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.
Claims15
An apparatus, comprising:
- a memory circuit including a global read selection line to provide a read voltage, a global program selection line to provide a program voltage, and a plurality of memory blocks, each block being coupled to the global read selection line and to the global program selection line, each block including
- a regional selection line and a plurality of local selection lines;
- a read transistor coupling the global read selection line to the regional selection line to switchably apply the read voltage to the regional selection line;
- a program transistor coupling the global program selection line to the regional selection line to switchably apply the program voltage to the regional selection line;
- and
- a plurality of local selection transistors, each coupling the regional selection line to one of the local selection lines.
A system, comprising:
- a memory system including a plurality of memory arrays, each memory array including a plurality of planes, each plane including
- a global read selection line to provide a read voltage, a global program selection line to provide a program voltage, and a plurality of memory blocks, each block being coupled to the global read selection line and to the global program selection line, each block including
- a regional selection line and a plurality of local selection lines;
- a read transistor coupling the global read selection line to the regional selection line to switchably couple the read voltage to the regional selection line;
- a program transistor coupling the global program selection line to the regional selection line to switchably couple the program voltage to the regional selection line;
- and
- a plurality of local selection transistors, each coupling the regional selection line to one of the local selection lines.
A method, comprising:
- performing a memory read operation in a first memory block by
- coupling a read voltage to a global read selection line extending to the first memory block and to a second memory block;
- switchably coupling the read voltage from the global read selection line to a first regional selection line in the first memory block;
- coupling the read voltage from the first regional selection line to a first local selection line in the first memory block;
- coupling the read voltage to a first selected memory cell connected to the first local selection line in the first memory block;
- and
- performing a memory program operation in the second memory block by
- coupling a program voltage to a global program selection line extending the first and second memory blocks;
- switchably coupling the program voltage from tie global program selection line to a second regional selection line in the second memory block;
- coupling the program voltage from the second regional selection line to a second local selection line in the second memory block;
- and
- coupling the program voltage to a second selected memory cell connected to the second local selection line in the second memory block.
Dependencies are inferred from the claim text.