Multi-level memory cell

A multi-level memory cell, comprising:

• a substrate having a first doped region, a second doped region, and a channel region located between the first doped region and the second doped region;
• a first floating gate located over the channel region near the first doped region;
• a second floating gate located over the channel region near the second doped region and isolated from the first floating gate;
• an insulating block having a first side and a second side, wherein the first side is connected to the first floating gate, and the second side is connected to the second floating gate;
• a control gate located over the first floating gate and the second floating gate;
• and
• an erasing gate located beside the first and the second floating gates;
• wherein the first doped region and the second doped region have different dosages and implant energies.

A multi-level memory cell, comprising:

• a substrate having a first doped region, a second doped region, and a channel region located between the first doped region and the second doped region;
• a first floating gate located over the channel region near the first doped region;
• a second floating gate located over the channel region near the second doped region and isolated from the first floating gate;
• and
• a control gate located over the first floating gate and the second floating gate,
• wherein the dosage of the first doped region is higher than that of the second doped region and the first and second doped regions have different implant energies,
• wherein when a high voltage applied to the control gate, a first bias voltage is applied to the second doped region to write a data “1”, a second bias voltage is applied to the first doped region to write a data “2”, and a third bias voltage is applied to the first doped region and then the second doped region to write a data “3”.