Nonvolatile ferroelectric memory device and method for driving the same

A method for driving a nonvolatile ferroelectric memory device that includes a main cell and a reference cell provided with one transistor and one or more ferroelectric capacitors among a first voltage applying line, which is a first wordline, a bitline and a second voltage applying line, the method comprising:

• first activating the first wordline and a reference wordline to a relatively high level in an active period of one cycle;
• inactivating the first wordline and the reference wordline;
• activating a sensing amplifier after the first wordline is inactivated;
• second or third activating the first wordline at a relatively high level in a state that the sensing amplifier is activated in the active period;
• activating the second voltage applying line to a relatively high level at least once during the active period and such that the activation of the second voltage applying line is coincident with the second or third activation of the first wordline at one point;
• and
• transiting a chip enable signal from a relatively low level to a relatively high level to precharge the chip enable signal.

A method for driving a nonvolatile ferroelectric memory device that includes a plurality of sub cell arrays provided with a plurality of main cells and a reference cell, the reference cell of any sub cell array of the plurality of sub sell arrays being operated together with the main cell of a neighboring sub cell array and each sub cell array including a transistor and at least one ferroelectric capacitor among a bitline, a first wordline, a reference wordline, and a plate line, the method comprising:

• first activating the first wordline, the reference wordline, the plate line, and a reference plate line to a relatively high level in an active period of one cycle;
• inactivating the first wordline and the reference wordline;
• activating a sensing amplifier after the first wordline is inactivated;
• second activating the first wordline to a relatively high level in a state that the sensing amplifier is activated during the active period;
• inactivating the plate line in a state that the first wordline is second activated;
• and
• transiting a chip enable signal from a relatively low level to a relatively high level to precharge the chip enable signal.

A method for driving a nonvolatile ferroelectric memory device that includes a plurality of main cell arrays arranged in row direction including wordlines of split structures having first and second split wordlines in pairs, a plurality of bitlines arranged across the first and second split wordlines, a reference cell including a transistor and at least one ferroelectric capacitor among a reference wordline, a reference plate line and the bitline, and a column selector arranged between a data line and the bitlines, the method comprising:

• first activating the first and second split wordlines, the reference wordline, and the reference plate line to a relatively high level in an active period of one cycle;
• inactivating the first and second split wordlines and the reference wordline;
• activating a sensing amplifier after the first split wordline is inactivated;
• second activating the second split wordline at a relatively high level during the active period;
• second and third activating the first split wordline in an order of a relatively high, a relatively low, and a relatively high level in a state that the sensing amplifier is activated and the second split wordline is second activated during the active period;
• and
• transiting a chip enable signal from a relatively low level to a relatively high level to precharge the chip enable signal.

A method for driving a nonvolatile ferroelectric memory device that includes a plurality of main cell arrays arranged in row direction including wordlines of split structures having first and second split wordlines in pairs, a plurality of bitlines arranged across the first and second split wordlines, a reference cell including a transistor and at least one ferroelectric capacitor among a reference wordline, a reference plate line and a bitline, and a column selector arranged between a data line and the bitlines, the method comprising:

• first activating the first and second split wordlines, the reference wordline, and the reference plate line at a relatively high level in an active period of one cycle;
• inactivating the first and second split wordlines and the reference wordline;
• activating a sensing amplifier after the first split wordline is inactivated;
• second activating the second split wordline during the active period in a step form of relatively high and boosted high level;
• second and third activating the first split wordline in the order of relatively high, relatively low, and boosted high level in a state that the sensing amplifier is activated and the second split wordline is second activated during the active period;
• and
• transiting a chip enable signal from a relatively low level to a relatively high level to precharge the chip enable signal.