Reduced area sense amplifier isolation layout in a dynamic RAM architecture
AssigneeMicron Technology, Inc.
InventorBrent Keeth
Life of this patent
Estimating the term…
Abstract
A memory device has an array of memory cells which are positioned in a first block and a second block. The memory cells are arranged in rows and columns. A plurality of bit lines is coupled to the memory cells and a plurality of word lines is coupled to the memory cells. A sense amplifier is positioned between the first block and the second block, and a plurality of electrical connections is made between the sense amplifier and the bit lines. A plurality of isolation transistors are electrically connected in series with the electrical connections, the isolation transistors being located within the first and second blocks and spaced from the sense amplifier block.
Claims10
A memory device comprising:
- an array of memory cells positioned in a first block and a second block, the memory cells being arranged in rows and columns;
- a plurality of bit lines electrically coupled to the memory cells;
- a plurality of word lines electrically coupled to the memory cells;
- a sense amplifier, in series with and electrically between the first block and the second block;
- a plurality of electrical connections between said sense amplifier and said bit lines;
- and
- a plurality of isolation transistors in series with said electrical connections, said isolation transistor being physically located within the first and second blocks and being physically spaced from said sense amplifier, said isolation transistors have source and drain regions having the same dimensions as source and drain regions of said memory cells.
An intergrate circuit structure in a memory device comprising:
- a substance of semiconductor material of first conductivity type;
- an array of memory cells on said substrate, said memory cells being arranged in rows and columns, said memory cells being positioned into blocks;
- a plurality of bit line pairs electrically coupled to the memory cells;
- a plurality of sense amplifiers in aid substrate, said sense amplifiers being physically positioned between blocks of memory cells;
- and
- a plurality of first isolation transistors being electrically connected in series between said sense amplifiers and said bit lines, aid isolation transistors being physically positioned within the block of memory cells within the array of memory cells, said isolation transistors being physically spaced from said sense amplifiers.
Dependencies are inferred from the claim text.