US 6,480,199 B1 · Image processing apparatus

Abstract

An image processing apparatus which can effectively use a storage circuit provided together with a logic circuit, perform high speed processing, and reduce the power consumption without causing a decline in the performance. The image processing system includes a DRAM for storing image data and a logic circuit, which are provided together on a semiconductor chip. The DRAM is divided into a plurality of DRAM modules, and the divided plurality of DRAM modules are arranged around a logic circuit portion for carrying out graphic drawing processing etc. When the ratio of valid data occupying bit lines in one access increases, the distances from the DRAM modules to the logic circuit portion become uniform, the length of the longest path interconnection can be made shorter comparing with the case of arrangement fixed in one direction, and the overall operating speed can be improved.

Claims36

Dependent claims

An image processing apparatus comprising:

a storage circuit, said storage circuit including a plurality of storage modules, a storage module of said plurality of storage modules storing a portion of an image, said portion of said image being stored as image data;
a control module, said control module controlling said plurality of storage modules;
and
a logic circuit, said logic circuit including a plurality of pixel processing modules, a pixel processing module of said plurality of pixel processing modules being associated with only one storage module of said plurality of storage modules, said pixel processing module processing said image data, said logic circuit processes said image data using said image data stored within said storage circuit,
wherein said storage circuit and said logic circuit are accommodated on one semiconductor chip.

2 more elements

An image processing apparatus for performing rendering by receiving polygon rendering data including three-dimensional coordinates (x, y, z), R (red), G (green), and B (blue) data, homogeneous coordinates (s, t) of texture, and a homogeneous term q for vertexes of a unit graphic comprising:

a storage circuit divided into a plurality of storage modules, each storage module storing display data of different pixels and texture data required by at least one graphic element;
a logic circuit comprising at least an interpolation data generating circuit for performing interpolation on the polygon rendering data of the vertexes of said unit graphic to generate interpolation data of pixels positioned inside said unit graphic and a texture processing circuit for dividing the homogeneous coordinates (s, t) of texture included in said interpolation data by the homogeneous term q to generate “s/q” and “t/q”, using texture addresses in accordance with said “s/q” and “t/q” to read texture data from said storage circuit, and performing processing for applying the texture data to the surface of the graphic elements of the display data,
said logic circuit including a plurality of pixel processing blocks and a control module,
said control module having a plurality of control module terminals,
each pixel processing block of said plurality of pixel processing blocks processing said image data,
a first processing block of said plurality of pixel processing blocks being connected to only a first storage module of said plurality of storage modules and being connected to a first control module terminal of said plurality of control module terminals;
said storage circuit and said logic circuit being both accommodated on one semiconductor chip.

4 more elements

Dependencies are inferred from the claim text.

Image processing apparatus

Life of this patent

Image processing apparatus

Life of this patent

Abstract

Claims36