Low power, no deadzone phase frequency detector with charge pump

Phase locked loop circuit for locking a clock signal to an input signal comprising a phase frequency detector (1) for supplying up pulse signals and down pulse signals to a charge pump (2), which charge pump comprises a set of current sources (3,4) and an idle path (5-C, 6-C, 7, 8) for maintaining current supplying transistors in the current sources (3, 4) in a current conductive state when no up and down pulse signals are present characterized in that first means (10, 12) are present for enabling and disabling the idle path (5-C, 6-C, 7, 8) in response to idle path enabling (41) and idle path disabling (42) signals, respectively and in that second means (20) are present for, shortly before an appearance of up and down pulse signals, respectively generating an idle path enabling signal (41) and for, shortly after the respective up and down signals have disappeared, generating an idle path disabling signal (42).