Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances
AssigneeIntel Corporation
InventorsSanjay Dabral, Krishna Seshan
Life of this patent
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Abstract
A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.
Claims9
An apparatus comprising:
- a first circuit and a different second circuit, each circuit comprising a plurality of transistor devices formed on a substrate;
- a first connection line between the plurality of transistor devices of the first circuit to carry a first signal;
- a second connection line between the plurality of transistor devices of the second circuit to carry a second signal synchronous with the first signal,
- wherein each of the first and second circuits comprises a plurality of transistor devices, at least one transistor device of each of the first and second circuits having a gate over a portion of an active area of the substrate, the gate having a gate width, Wg, measured across a width of the active area of a substrate, and at least a first leg and a second leg of a width, Wl,
- wherein Wl is equal to Wg,
- divided by the number of legs, n,
- wherein the distance between the first leg and the second leg is a multiple, m, of the target dimension of Wg,
- wherein m is determined to minimize a line proximity effect.
Dependencies are inferred from the claim text.