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US 6,480,054 B2Granted
Digital electronic circuit for use in implementing digital logic functions
OwnerDzung Joseph Tran, Mark W. Acuffinventors
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Abstract
A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.
Claims20
A digital electronic circuit comprising:
- a first section adapted to transmit one of N input signals;
- and
- a second section associated with the first section to receive the signal transmitted by the first section, where the second section includes a first P-channel/N-channel transistor pair controllable by a first control signal, a second P-channel/N-channel transistor pair controllable by a second control signal, and a third P-channel/N-channel transistor pair controllable by the signal transmitted by the first section;
- where the second section is selectively configurable either to output an inverse of the signal transmitted by the first section or a logical 0 in reponse to the control signals, or to output an inverse of the signal transmitted by the first section or a logical 1 in response to the control signals.
1 more element
A CMOS digital electronic circuit, comprising:
- a first section adapted to transmit one of N input signals;
- and
- a second adapted to receive the signal transmitted by the first section, a first control signal, and a second control signal;
- wherein the second section includes no more than six transistors and an output node, and
- wherein the second section is selectively configurable to output a signal Q to the output node corresponding to one of the following Boolean equations:
- Q={overscore (I+XY)}Q={overscore (I(X+Y))}Q={overscore (I+X)}Q={overscore (IX)}
- where I is the signal transmitted by the first section, X is the first control signal, and Y is the second control signal.
4 more elements
A method of digital electronic circuit design to produce desired digital output values in response to combinations of five digital input values (I1, I2, S1, X, Y), the method comprising:
- deciding upon a plurality of digital output values Q, one for each combination of digital input values;
- selecting a CMOS circuit having at least one selectively configurable section comprising no more than twelve transistors, wherein the section includes five input signal nodes and at least one output signal node;
- configuring the section to output Q at the output signal node according to the combination of digital input values at the corresponding input signal nodes;
- and
- wherein Q is represented by the following truth table:
- S1 X Y Q 0 0 0 {overscore (I1)} 0 0 1 {overscore (I1)} 0 1 0 {overscore (I1)} 0 1 1 0 1 0 0 {overscore (I2)} 1 0 1 {overscore (I2)} 1 1 0 {overscore (I2)} 1 1 1 0.
3 more elements
A method of digital electronic circuit design to produce desired digital output values in response to combinations of five digital input values (I1, I2, S1, X, Y), the method comprising:
- deciding upon a plurality of digital output values Q, one for each combination of digital input values;
- selecting a CMOS circuit having at least one selectively configurable section comprising no more than twelve transistors, wherein the section includes five input signal nodes and at least one output signal node;
- configuring the section to output Q at the output signal node according to the combination of digital input values at the corresponding input signal nodes;
- and
- wherein Q is represented by the following truth table:
- S1 X Y Q 0 0 0 1 0 0 1 {overscore (I1)} 0 1 0 {overscore (I1)} 0 1 1 {overscore (I1)} 1 0 0 1 1 0 1 {overscore (I2)} 1 1 0 {overscore (I2)} 1 1 1 {overscore (I2)}.
3 more elements
A method of digital electronic circuit design to produce desired digital output values in response to combinations of five digital input values (I1, I2, S1, X, Y), the method comprising:
- deciding upon a plurality of digital output values Q, one for each combination of digital input values;
- selecting a CMOS circuit having at least one selectively configurable section comprising no more than twelve transistors, wherein the section includes five input signal nodes and at least one output signal node;
- configuring the section to output Q at the output signal node according to the combination of digital input values at the corresponding input signal nodes;
- and
- wherein Q is represented by the following truth table:
- S1 X Y Q 0 0 — {overscore (I1)} 0 1 — 0 1 0 — {overscore (I2)} 1 1 — 0.
3 more elements
A method of digital electronic circuit design to produce desired digital output values in response to combinations of five input values (I1, I2, S1, X, Y), the method comprising:
- deciding upon a plurality of digital output values Q, one for each combination of digital input values;
- selecting a CMOS circuit having at least one selectively configurable section comprising no more than twelve transistors, wherein the section includes five signal nodes and at least one output signal node;
- configuring the section to output Q at the output signal node according to the combination of digital input values at the corresponding input signal nodes;
- and
- wherein Q is represented by the following truth table:
- S1 X Y Q 0 0 — 1 0 1 — {overscore (I1)} 1 0 — 1 1 1 — {overscore (I2)}.
3 more elements
A circuit comprising:
- a serial cascade TGM multiplexer having N input nodes, a multiplexer output node, and N-1 select nodes, where the multiplexer is configured to output a selected input signal to the multiplexer output node, depending on signals at the select nodes, without feedback or fan-out of the selected input signal;
- a first P-channel transistor having a drain, a source connected to VDD, and a gate connected to a first control node;
- a second P-channel transistor having a drain, a source connected to the drain of the first P-channel transistor, and a gate connected to a second control node;
- a third P-channel transistor having a source, a drain, and a gate connected to the multiplexer output node;
- a first N-channel transistor having a drain, a source connected to Ground, and a gate connected to the first control node;
- a second N-channel transistor having a drain, a source connected to the drain of the first N-channel transistor, and a gate connected to the second control node;
- third N-channel transistor having a source, a drain, and a gate connected to the multiplexer output node;
- and
- circuit output node connected to the drains of the third P-channel and third N-channel transistors, and not coupled to any of the N input nodes of the serial cascade TGM multiplexer to avoid feedback.
6 more elements
A circuit comprising:
- a multiplexer having a plurality of TGM stages configured in a serial cascade arrangement, wherein each TGM stage is adapted to receive two input signals selectable by a separate select signal and to output a selected one of the two input signals, and wherein each TGM stage is configured without internal feedback or fan-out of the signal output from that TGM stage;
- a circuit output node configured to output a final output signal;
- a first P-channel transistor having a drain, a source connected to VDD, and a gate connected to a control node;
- another P-channel transistor having a source connected to the drain of the first P-channel transistor, a drain connected to the circuit output node, and a gate connected to the multiplexer output node;
- a first N-channel transistor having a drain connected to the circuit output node, a source connected to Ground, and a gate connected to the control node;
- and
- another N-channel transistor having a source connected Ground, a drain connected to the circuit output node, and a gate connected to the multiplexer output node;
- where the circuit output node is not coupled to input the final output signal to the TGM stages of the multiplexer to avoid feedback.
5 more elements
A circuit comprising:
- a multiplexer having a plurality of TGM stages configured in a serial cascade arrangement, wherein each TGM stage is adapted to receive two input signals selectable by a separate select signal and to output a selected one of the input signals, and wherein each TGM stage is configured without internal feedback or fan-out of the signal output from that TGM stage;
- circuit output node configured to output a final output signal;
- a first P-channel transistor having a source connected to VDD, a drain connected to a circuit output node, and a gate connected to a control node;
- another P-channel transistor having a source connected to VDD, a drain connected to the circuit output node, and a gate connected to the multiplexer output node;
- a first N-channel transistor having a drain, a source connected to Ground, and a gate connected to the control node;
- and
- another N-channel transistor having a source connected to the drain of the first N-channel transistor, a drain connected to the circuit output node, and a gate connected to the multiplexer output node;
- wherein the circuit output node is not coupled to input the final output signal to the TGM stages of the multiplexer to avoid feedback.
5 more elements
Dependencies are inferred from the claim text.