Parasitic capacitance canceling circuit
AssigneeCypress Semiconductor Corporation
InventorFred-Johan Pettersen
Life of this patent
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Abstract
A circuit than may be used in an integrated circuit capacitor design. The circuit generally comprises a multilayer capacitor and a buffer. The multilayer capacitor may be configured as (i) a first capacitance, (ii) a second capacitance, and (iii) a third capacitance in series between the first capacitance and the second capacitance. The buffer may be configured to maintain a constant voltage across the third capacitance to isolate the first capacitance from the second capacitance.
Claims14
A circuit comprising:
- a multilayer capacitor configured as (i) a first capacitance, (ii) a second capacitance, and (iii) a third capacitance in series between said first capacitance and said second capacitance;
- and
- a buffer connected between (a) a first node common to said first and third capacitances and (b) a second node common to said second and third capacitances, said buffer configured to maintain a constant voltage of approximately zero volts across said third capacitance to (i) isolate said first capacitance from said second capacitance and (ii) minimize a leakage current through said third capacitance.
A method for isolating a first capacitance from a second capacitance in a multilayer capacitor comprising the steps of:
- (A) providing a third capacitance between said first capacitance and said second capacitance;
- and
- (B) maintaining a constant voltage of approximately zero volts across said third capacitance to minimize a leakage current through said third capacitance.
A circuit comprising:
- means for providing a multilayer capacitor configured as (i) a first capacitance, (ii) a second capacitance, and (iii) a third capacitance in series between said first capacitance and said second capacitance;
- and
- means for maintaining a constant voltage of approximately zero volts across said third capacitance to (i) isolate said first capacitance from said second capacitance and (ii) minimize a leakage current through said capacitance.
Dependencies are inferred from the claim text.