Level shifter with no quiescent DC current flow

A level shifter comprising a current mirror having a circuit node for receiving a current controlled by a control current applied at a control node thereof, said current mirror being selectively connected to a supply terminal via a PMOS supply switch, the level shifter further comprising a first PMOS switch connected to said control node for selectively applying said control current in response to an input logic signal at an input node, a second NMOS switch for selectively pulling down said circuit node in response to said input logic signal, and connecting circuitry connecting said circuit node to a control terminal of said supply switch, wherein said current mirror comprises first and second PMOS transistors having common drain/source terminals, the first PMOS transistor having a source/drain terminal in common with its gate terminal as said control node, and the second PMOS transistor having a gate terminal in common with the gate terminal of the first PMOS transistor and a source/drain terminal as said circuit node, and wherein the level shifter further comprises a further first switch and a further second switch connected to said first switch and said second switch respectively to realize therewith a logic function.

A level shifter comprising a current mirror having a circuit node for receiving a current controlled by a control current applied at a control node thereof, said current mirror being selectively connected to a supply terminal via a supply switch, the level shifter further comprising a first switch connected to said control node for selectively applying said control current in response to an input logic signal at an input node, a second switch for selectively pulling down said circuit node in response to said input logic signal and connecting circuitry connecting said circuit node to a control terminal of said supply switch, wherein said connecting circuitry provides a direct electrical connection without any active components between said circuit node and said control terminal of said supply switch.

A level shifter comprising a current mirror having a circuit node for receiving a current controlled by a control current applied at a control node thereof, said current mirror being selectively connected to a supply terminal via a PMOS supply switch, the level shifter further comprising a first NMOS switch connected to said control node for selectively applying said control current in response to an input logic signal at an input node, a second NMOS switch for selectively pulling down said circuit node in response to said input logic signal, and connecting circuitry connecting said circuit node to a control terminal of said supply switch, wherein said current mirror comprises first and second PMOS transistors having common drain/source terminals, the first PMOS transistor having a source/drain terminal in common with its gate terminal as said control node, and the second PMOS transistor having a gate terminal in common with the gate terminal of the first PMOS transistor and a source/drain terminal as said circuit node, and wherein said connecting circuitry provides a direct electrical connection without any active components between said circuit node and said control terminal of said supply switch.