Multiphase clock generator
AssigneeInternational Business Machines Corporation
InventorsDavid William Boerstler, Robert Keven Montoye, Kevin John Nowka
Life of this patent
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Abstract
The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.
Claims48
An apparatus for generating a quadrature clock of frequency F corresponding to a reference clock of frequency F comprising:
- a voltage controlled oscillator with M-phase outputs (MPVCO) having frequency F/N set in response to a control voltage where N is greater than one;
- an M-output phase detector (MPD) receiving said reference clock and said M-phase outputs of said MPVCO, said MPD generating M-detector outputs in response to 2M-sampled phase outputs of said M-phase outputs and said reference clock;
- a Sync State logic circuit receiving said M-detector outputs of said MPD, said Sync State logic circuit generating M-Sync State outputs and an error signal, said error signal processed to generate said control voltage;
- and
- a quadrature logic circuit receiving said M-phase outputs and said M-Sync State outputs, said quadrature logic circuit generating a quadrature clock with a frequency F corresponding to said reference clock in response to said M-phase outputs and said M-Sync State outputs.
A method for generating a quadrature clock of frequency F corresponding to a reference clock of frequency F comprising:
- generating M-phase outputs in an M-phase voltage-controlled oscillator (MPVCO) having frequency F/N set in response to a control voltage where N is greater than one;
- generating M-phase detector outputs in an M-output phase detector (MPD) receiving said reference clock and said M-phase outputs of said MPVCO, said MPD generating M-detector outputs in response to 2M-sampled phase outputs of said M-phase outputs and said reference clock;
- generating M-Sync State outputs and an error signal in a Sync State logic circuit receiving said M-detector outputs of said MPD, said error signal processed to generate said control voltage;
- and
- generating a quadrature clock with a frequency F corresponding to said reference clock in a quadrature logic circuit receiving said M-phase outputs and said M-Sync State outputs.
An integrated circuit (IC) for generating a quadrature clock of frequency F corresponding to a reference clock of frequency F comprising:
- a voltage controlled oscillator with M-phase outputs (MPVCO) having frequency F/N set in response to a control voltage where N is greater than one;
- an M-output phase detector (MPD) receiving said reference clock and said M-phase outputs of said MPVCO, said MPD generating M-detector outputs in response to 2M-sampled phase outputs of said M-phase outputs and said reference clock;
- a Sync State logic circuit receiving said M-detector outputs of said MPD, said Sync State logic circuit generating M-Sync State outputs and an error signal, said error signal processed to generate said control voltage;
- and
- a quadrature logic circuit receiving said M-phase outputs and said M-Sync State outputs, said quadrature logic circuit generating a quadrature clock with a frequency F corresponding to said reference clock in response to said M-phase outputs and said M-Sync State outputs.
Dependencies are inferred from the claim text.