Circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal

#The invention relates to a circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal.

#Such a circuit is known from German patent document 43 15 298. The circuit described therein requires an inverter with an additional clock circuit whose frequency must be related to the frequency of the signal to be inverted. The clock signal determines the tempo in which and the moments at which the edges of the digital signal and the inverted signal are synchronized by means of the circuit disclosed. A digital signal having edges at moments not related to the edges of the clock signal cannot be inverted with the circuit under discussion in such a manner that the edges, and possibly the steepnesses thereof, of the digital signal and the inverted signal are representative of the original signal.

#Timing may be highly critical in circuits on occasions in the sense that a signal must be available in the normal as well as the inverse form simultaneously, such that no delay obtains between the edges of the two signals. That is to say, the edges of the two signals must exactly coincide in time.

#The invention will now be explained in more detail below with reference to he accompanying drawings, in which:

#FIG. 1 shows a circuit according to the invention; and

#FIG. 2 shows an application of a circuit according to the invention in a wider environment for controlling greater loads.

#FIG. 1 shows the circuit with a supply voltage+Vcc and ground connection 1.

#A first inverter 2 and a second inverter 3 are connected in series between an input 4 of the circuit and a first output 5 of the circuit. The inverters 2 and 3 each comprise a P-type MOS-FET 6 and 7, respectively, whose sources are connected to the supply voltage+Vcc, whose gates are connected to the gates of respective N-type MOS-FETs 8 and 9, the sources of said N-type MOS-FETs being connected to ground 1. The drains both of the P-type MOSFET 6 and the N-type MOS-FET 8, and those of the P-type MOS-FET 7 and N-type MOS-FET 9 are interconnected. The input 4 of the circuit is connected to a junction point 10 of the gates of the P-type MOS-FET 6 and the N-type MOS-FET 8. A junction point 11 is formed by the interconnection of the drain of the P-type MOS-FET 6, the drain of the N-type MOS-FET 8, the gate of the P-type MOS-FET 7, and the gate of the N-type MOS-FET 9. A junction point 12 of the drains of the P-type MOS-FET 7 and the N-type MOS-FET 9 is connected to the first output 5. The circuit further comprises a P-type MOS-FET 13 and an N-type MOS-FET 14. The gate of the P-type MOS-FET 13 is connected to the gate of the N-type MOS-FET 14 in a junction point 15. Said junction point 15 is connected to the junction point 10. The source of the P-type MOS-FET 13 is connected to the source of the N-type MOS-FET 14 in a junction point 16. Said junction point 16 is connected to the junction point 11. The drain of the P-type MOS-FET 13 is connected to the drain of the N-type MOS-FET 14 in a junction point 17. Said junction point 17 is connected to a second input 18 of the circuit. The substrate of the P-type MOS-FET 13 is connected to the supply voltage+Vcc and is not connected to the source of the P-type MOS-FET 13. It is not indicated for the sake of clarity that the substrate of the N-type MOS-FET 14 is connected to ground 1.

#The operation of the circuit of FIG. 1 is as follows. Let us suppose that the signal at the input 4 of the circuit switches from low to high. This has the result that the potential at the junction points 10 and 15 becomes high. The fact that the potential at the junction point 15 becomes high switches the P-type MOS-FET 13 off and switches the N-type MOS-FET 14 on. This, however, does not yet have any consequences for the signal at junction point 17 and output 18. The potential at the junction point 11 switches from high to low with a delay determined by the P-type MOS-FET 6 and the N-type MOS-FET 8. The switch from high to low of the potential at the junction point 11 has two consequences. The first consequence relates to the inverter 3. The potential at the junction point 12, and thus at the first output 5 of the circuit, becomes high with a delay determined by the P-type MOS-FET 7 and the N-type MOS-FET 9. The switch from high to low of the potential at the junction point 11, and accordingly at the junction point 16, has a consequence for the circuit formed by the P-type MOS-FET 13 and N-type MOS-FET 14, i.e. that the potential at the junction point 17, and accordingly at the second output 18 of the circuit, drops in accordance with the switching-off of the P-type MOS-FET 13 and the switching-on of the N-type MOSFET 14. It should be borne in mind here that both the switch from low to high of the potential at the junction point 12 and the switch from high to low of the potential at the junction point 17 do not take place until the moment the potential at the junction point 11/16 has dropped to below a threshold value. It should be noted that the gate-source voltages of the N-type MOSFET 14 and the P-type MOS-FET 7 remain unchanged during this process.