Reduced jitter phase lock loop using a technique multi-stage digital delay line

A digital phase locked loop for generating a stable output clock signal from at least one reference frequency signal, comprising:

• a phase detector for detecting a phase difference between said reference frequency signal and said stable clock signal and producing a phase error signal representative of the phase difference;
• a digital controlled oscillator for receiving said phase error signal and generating an output signal at a desired frequency and a control signal representing a time error in said output signal;
• a stable local oscillator for providing clock signal to said digital controlled oscillator;
• a plurality of tapped delay lines for generating said stable output clock signal, each of said tapped delay lines comprising a plurality of delay elements, the sum of the delay of each of said plurality of tapped delay lines being less than the period of said output signal of said digital controlled oscillator;
• each of said plurality of tapped delay lines having a coarse, tapped delay line for receiving the output signal of said digital controlled oscillator;
• and a fine, tapped delay line for receiving the output signal of said coarse tapped delay line, said fine tapped delay line having a plurality of delay elements having a delay time proportional to one of said coarse tapped delay elements;
• a plurality of ring oscillators each one having a plurality of said tapped delay elements for producing a clock signal;
• and
• a plurality of counter/scaler devices to integrate the clock output signal of said plurality of ring oscillators and produce a control output signal for calibrating said control signal of said digital controlled oscillator.

A frequency synthesizer for synthesizing a stable output clock signal from a reference clock signal comprising:

• a digital controlled oscillator for receiving said reference clock signal and generating an output signal at a desired frequency and a control signal representing a time error in said output signal;
• a stable lock oscillator for providing a clock signal to said digital controlled oscillator;
• a plurality of tapped delay lines for generating said output clock signal, each of said tapped delay lines having a plurality of delay elements, the sum of the delay of each of said plurality of tapped delay lines being less than the period of said output signal of said digital controlled oscillator;
• each of said plurality of tapped delay lines including a coarse, tapped delay line for receiving the output signal of said digital controlled oscillator;
• and a fine, tapped delay line for receiving the output signal of said coarse tapped delay line, said fine tapped delay line comprising a plurality of delay elements having a delay time proportional to one of said coarse tapped delay elements;
• a plurality of ring oscillators each one comprising a plurality of said tapped delay elements for producing a clock output signal;
• and
• a plurality of counter/scaler devices to integrate the clock output signal of said plurality of ring oscillators and produce a control output signal for calibrating said control signal of said digital controlled oscillator;
• wherein said digital controlled oscillator is an adding type rate multiplier that generates said output signal when attaining an overflow condition, a remainder term upon attainment of said overflow condition generating said control signal.

A method of synthesizing a frequency from a clock reference comprising the steps of:

• generating lock clock signals with a stable oscillator;
• clocking a digital controlled oscillator with said local clock signals;
• feeding a first output of said digital controlled oscillator to a first tapped delay line;
• feeding an output of said first tapped delay line to second tapped delay line;
• wherein said second tapped delay line has a delayed time proportional relationship to said first tapped delay line;
• generating a delay measuring ratio signal with a ring oscillator said ring oscillator having a delay proportional to said first and second tapped delay lines;
• correcting a second output of said digital controlled oscillator with said delay measuring ratio signal to generate a corrected time error signal in said first output of said digital controlled oscillator;
• controlling said first and second tapped delay lines with said corrected time error signal to generate clock signals at desired frequencies having a precision greater than one clock cycle of said stable oscillator.