Digital frequency multiplier
AssigneeThomson Licensing
InventorDavid Lawrence Albean
Life of this patent
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Abstract
A digital frequency multiplier provides non-integer frequency multiplication of an input signal. A multiplexer receives the input signal and an integer multiple of the input signal. A multiplexer control signal selects/toggles which signal the multiplexer will output and how long. A counter, clocked by one of the signals, provides the multiplexer control signal. The multiplexer outputs a pre-determined number of clock cycles of each signal to produce the desired non-integer frequency multiplied input signal. The present invention generates frequency multiplication without a phase locked loop (PLL).
Claims20
A digital frequency multiplier comprising:
- frequency multiplying means for receiving an input signal of a given frequency and generating an intermediate signal of a frequency that is an integer multiple of the given frequency of the input signal;
- signal selection means in communication with the frequency multiplying means for receiving the input signal and the intermediate signal and selectively outputting the input signal for a first predetermined period of time and the intermediate signal for a second predetermined period of time in response to a control signal to generate an output signal having a frequency that is a non-integer multiple of the given frequency of the input signal;
- and
- control means in communication with the signal selection means for generating the control signal and operable for providing the control signal to the signal selection means, said control means being adapted to receive said intermediate signal and to generate said control signal in response thereto to said signal selection means so that said control means generates a control signal for an appropriate number of clock cycles for both said input signal and for said intermediate signal.
A digital frequency multiplier comprising:
- a frequency multiplier unit operable to generate an intermediate signal having a frequency that is an integer multiple of a frequency of an input signal;
- a multiplexer having a first input in communication with the frequency multiplier unit and operable to receive the intermediate signal, and a second input operable to receive the input signal, the multiplexer configured to output the intermediate signal for a predetermined period of time in response to a control signal of a first state, and output the input signal for a predetermined period of time in response to a control signal of a second state, wherein the selective outputting of the intermediate signal and the input signal results in an output signal of a frequency that is a non-integer multiple of the input signal;
- and
- a control signal generator in communication with the multiplexer and operable to generate the control signal of the first state and the control signal of the second state, said control signal generator being adapted to receive said intermediate signal and to generate said control signal in response thereto for said signal selection means so that said control means generates a control signal for an appropriate number of clock cycles for both said input signal and for said intermediate signal.
A method of generating an output signal of a frequency that is a non-integer multiple of a frequency of an input signal comprising:
- digitally generating an intermediate signal of a frequency that is an integer multiple of the frequency of the input signal;
- determining a first number of clock cycles of the input signal and a second number of clock cycles of the intermediate signal that, when combined, generate an output signal of a frequency that is the non-integer multiple of the frequency of the input signal;
- digitally generating a control signal indicative of the first number of clock cycles and the second number of clock cycles, said control signal being generated in response to receipt of said intermediate signal so that said control signal is generated for an appropriate number of clock cycles for both said input signal and for said intermediate signal;
- and
- digitally selectively outputting the input signal for the first number of clock cycles and the intermediate signal for the second number of clock cycles in response to the control signal, whereby the selective outputting of the input signal and the intermediate signal results in an output signal of a frequency that is a non-integer multiple of the frequency of the input signal.
Dependencies are inferred from the claim text.