US 6,480,036 B2Granted

Settable digital CMOS differential sense amplifier

AssigneeCompaq Information Technologies Group, L.P.

InventorsDaniel W. Bailey, Mark D. Matson

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Abstract

A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Claims23

Dependent claims

A computer system, comprising:

a central processing unit connected to a memory system by a system bus;
an I/O system, connected to the system bus by a bus interface device;
and
at least one sense amplifier, for sensing a first and second logic level of a first data signal and a second data signal contained in said central processing unit and for outputting representations of that logic level on complementary output terminals, said sense amplifier including:
a first discharge path, connected to a first one of said output terminals, for allowing a charge stored on said first one of said output terminals to be discharged at a first rate that is proportional to a voltage level developed on said first data signal;
a second discharge path, connected to a second one of said output terminals, for allowing a charge stored on said second one of said output terminals to be discharged at a second rate that is proportional to a voltage level developed on a second data signal;
a set and reset circuit for overriding said discharge of said first one of said output terminals in response to an assertion of a first control signal and for overriding said discharge of said second one of said output terminals in response to an assertion of a second control signal;
a pre-charge unit coupled to said first and second output terminals to pre-charge said first and second output terminals with the charges;
and
first and second disabling circuits cross-coupled to said output terminals and in said first and second discharge paths, respectively, to disable, as a function of the discharge rates, said first or second output terminal from discharging.

7 more elements

A computer system comprising:

a central processing unit connected to a memory system by a system bus;
an I/O system connected to the system bus by a bus interface device;
and
at least one sense amplifier for sensing a logic level of a first data signal and for outputting representations of that logic level on complementary output terminals, the sense amplifier including:
means for setting a first one of said complementary output terminals to a logic high level in response to an assertion of a first control signal;
means for resetting said first one of said complementary output terminals to a logic low level in response to an assertion of a second control signal;
a first discharge means for allowing a charge stored on said first one of said complementary output terminals of said sense amplifier to be discharged at a first rate that is proportional to a voltage level developed on said first control signal when said first control signal is asserted, said discharging of said charge stored on said first one of said complementary output terminals overriding effects imposed on said first one of said complementary output terminals by a first data signal;
a second discharge means for allowing a charge stored on a second one of said complementary output terminals to be discharged at a second rate that is proportional to a voltage level developed on said second control signal when said second control signal is asserted, said discharging of said charge stored on said second one of said complementary output terminals overriding effects imposed on said second one of said complementary output terminals by a second data signal, said first and second discharge means connected by a pull-up unit;
means for pre-charging said complementary output terminals with the charges;
and
first and second disabling means cross-coupled to said second and first discharge means and in series with said first and second discharge means, respectively, to disable, as a function of the discharge rates, said first or second one of said complementary output terminals from discharging.

8 more elements

In a computer system having a central processing unit connected to a memory system by a system bus and an I/O system connected to the system bus by a bus interface device, a method for sensing a logic level of a first data signal and for outputting representations of that logic level on complementary output terminals and for setting and resetting those output terminals, the method comprising:

setting a first one of said complementary output terminals to a logic high level in response to an assertion of a first control signal;
resetting said first one of said complementary output terminals to a logic low level in response to an assertion of a second control signal, said first control signal and said second control signal not being asserted at the same time;
discharging a charge stored on said first one of said complementary output terminals of said sense amplifier at a first rate that is proportional to a voltage level developed on said first control signal when said first control signal is asserted, said discharging of said charge stored on said first one of said complementary output terminals overriding effects imposed on said first one of said complementary output terminals by a first data signal;
and
discharging a charge stored on said second one of said complementary output terminals at a second rate that is proportional to a voltage level developed on said second control signal when said second control signal is asserted, said discharging of said charge stored on said second one of said complementary output terminals overriding effects imposed on said second one of said complementary output terminals by a second data signal;
detecting which of said first and second one of said complementary output terminals discharges at a faster rate;
and
based on which output terminal discharges at a faster rate, disabling the other output terminal from discharging.

5 more elements

Dependencies are inferred from the claim text.