Bus configuration and input/output buffer
AssigneeFujitsu Limited
InventorMasao Taguchi
Life of this patent
Estimating the term…
Abstract
A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.
Claims10
An input buffer circuit connected to a bus for receiving signals from said bus, said input buffer comprising:
- a first buffer receiving said signals, said first buffer operating in a first mode in which said signals are transmitted on said bus through a first frequency;
- a second buffer receiving said signals, said second buffer operating in a second mode in which said signals are transmitted on said bus through a second frequency lower than said first frequency;
- and
- means for providing one of an output of said first buffer and an output of said second buffer to an internal circuit,
- wherein power consumption of said second buffer during operation thereof is lower than power consumption of said first buffer during operation thereof, and wherein said first buffer comprises a first differential amplifier for determining levels of said signals through comparison with a reference voltage, and wherein said second buffer operates in said first mode in addition to said second mode and comprises a second differential amplifier for determining said levels of said signals through comparison with said reference voltage, said second differential amplifier being connected in parallel with said first buffer and having transistors with a narrower gate width than transistors of said first differential amplifier.
A DRAM comprising:
- a circuit unit configured to generate a control signal based on information stored in a register;
- a first buffer for receiving data signals transmitted through a first frequency in a first mode, said first buffer being controlled by said control signal to operate in said first mode;
- a second buffer for receiving the date signals transmitted through the first frequency in the first mode and for receiving data signals transmitted through a second frequency lower than said first frequency in a second mode;
- a circuit unit configured to provide an output of said first buffer and an output of said second buffer to an internal circuit.
An input buffer circuit receiving a signal, comprising:
- a first differential amplifier having a pair of first transistors, one of which receives said signal and the other of which receives a reference signal, the first differential amplifier comparing levels of said signal and reference signal in a first mode in which the signal has a small amplitude;
- a second differential amplifier having a pair of second transistors with narrower gate widths than said first transistors, one of which receives said signal and the other of which receives said reference signal, and the second differential amplifier compares said signal and reference signal in a second mode in which the signal has a large amplitude;
- and
- a buffer circuit coupled to said first and second differential amplifiers for outputting an output signal to an internal circuit.
Dependencies are inferred from the claim text.