Printed circuit assembly having integrated resistors for terminating data and control lines of a host-peripheral interface

An integrated circuit for a host-peripheral interface via which digital data are synchronously transmitted at a data rate via conductive paths that exhibit transmission-line characteristics at the data rate, the integrated circuit comprising:

• a first integrated-circuit terminal and a first connector terminal;
• a first transmission line for transmission of a data signal;
• a second integrated-circuit terminal and a second connector terminal;
• a second transmission line for transmission of a clocking signal;
• a first pad and a second pad;
• a first digital circuit for propagating the data signal through the first pad;
• a second digital circuit for propagating the clocking signal through the second pad;
• the first transmission line including a first integrated-circuit conductive path including a first integrated-circuit resistive element connected in series between the first pad and the first digital circuit, the first integrated resistive element comprising at least one first n-type portion and at least one first p-type portion, the first n-type portion including material doped with an n-type dopant and the first p-type portion including material doped with a p-type dopant, the first n-type portion and the first p-type portion being electrically coupled to one another via a first metal layer, the first n-type portion comprising a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled to the first n-type layer by the first metal layer;
• the second transmission line including a second integrated-circuit conductive path including a second integrated-circuit resistive element;
• the first integrated-circuit element having a first ohmic value and the second integrated-circuit element having a second ohmic value, each of the first and second ohmic values being of a magnitude that substantially matches a characteristic impedance of the conductive paths at the data rate.

A printed circuit board assembly comprising:

• an integrated-circuit terminal and a connector terminal;
• a printed-circuit conductive path connecting the integrated circuit terminal and the connector terminal;
• integrated circuitry including:
• a pad;
• a digital circuit for propagating the signal through the pad;
• an integrated-circuit conductive path connecting the pad to the integrated circuit terminal, the integrated circuit conductive path including an integrated-circuit resistive element connected in series between the pad and the digital circlet, the integrated-circuit resistive element including at least one first portion doped with an n-type dopant electrically coupled to and separated from at least one second portion doped with a p-type dopant, the first portion doped with the n-type dopant comprising a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled with first n-type layer via a metal layer.

An integrated circuit for a host-peripheral interface via which digital data are synchronously transmitted at a data rate via Conductive paths that exhibit transmission-line characteristics at the data rate, the integrated circuit comprising:

• a first integrated-circuit terminal and a first connector terminal;
• a first transmission line for transmission of a data signal;
• a second integrated-circuit terminal and a second connector terminal;
• a second transmission line for transmission of a clocking signal;
• a first pad and a second pad;
• a first digital circuit for propagating the data signal through the first pad;
• a second digital circuit for propagating the clocking signal through the second pad;
• the first transmission line including a first integrated-circuit conductive path including a first integrated-circuit resistive element connected in series between the first pad and the first digital circuit;
• the second transmission line including a second integrated-circuit conductive path including a second integrated-cicuit resistive element, the second integrated resistive element comprising at least one second n-type portion and at least one second p-type portion, the second n-type portion including material doped with an n-type dopant and the second p-type portion including material doped with a p-type dopant, the second n-type portion and the second p-type portion being electrically coupled to one another via a second metal layer, the second n-type portion comprising a third n-type layer including material doped with the n-type dopant and a fourth n-type layer including material doped with the n-type dopant, the fourth n-type layer being electrically coupled to the third n-type layer by the second metal layer;
• the first integrated-circuit element having a first ohmic value and the second integrated-circuit element having a second ohmic value, each of the first and second ohmic values being of a magnitude that substantially matches a characteristic impedance of the conductive paths at the data rate.